Developers can now deliver crystal-clear multiformat video at up to 1080 p H.264 at 30 fps (encode and closed-looped decode) in their digital video designs without concerns of video format support, constrained network bandwidth, limited system storage capacity or cost with the new TMS320DM369 DaVinci™ video processors from TI.
The DM369 device is uniquely capable of running TI’s third-generation noise filtering technology while achieving low-light HD H.264 720p30 video compression and is pin-to-pin compatible with the DM365 processors, using the same ARM ARM926EJ-S core running at 432 MHz. This ARM9-based DM369 device supports production-qualified H.264BP/MP/HP, MPEG-4, MPEG-2, MJPEG, and WMV9 (VC-1) codecs providing customers with the flexibility to select the correct video codec for their application. These codecs run on independent coprocessors (HDVICP and MJCP) offloading all compression needs from the main ARM core. This lets developers obtain optimal performance from the ARM for their applications, including their multichannel, multistream, and multiformat needs.
Video surveillance designers achieve greater compression efficiency to provide more storage without straining the network bandwidth. Developers of media playback and camera-driven applications, such as video doorbells, digital signage, digital video recorders, portable media players, and more can take advantage of the low power consumption and can ensure interoperability and product scalability by taking advantage of the full suite of codecs supported on the DM369 device.
Along with multiformat HD video, the DM369 processor also features a suite of peripherals that reduces system cost and complexity, thus enabling a seamless interface to most additional external devices required for video applications. The image sensor interface is flexible enough to support CCD, CMOS, and various other interfaces such as BT.656, BT1120. The DM369 device also offers a high level of integration with HD display support, including three built-in 10-bit HD analog video digital-to-analog converters (DACs), DDR2/mDDR, Ethernet MAC, USB 2.0, integrated audio, host port interface (HPI), analog-to-digital converter (ADC), and many more features that reduce overall system costs and save real estate on circuit boards, thus allowing for a
High-Performance Digital Media System-on-Chip (DMSoC)
432-MHz ARMARM926EJ-S Clock Rate
4:2:2 (8- and 16-Bit) Interface
Capable of 1080 p 30 fps H.264 Video Processing
Pin Compatible With DM365, DM368, DMVA1, and DMVA2 Processors
Fully Software-Compatible With ARM9
Extended Temperature Available for 432-MHz Device
Supports TI Third-Generation Noise Filter
Supports SMART Codec Feature for Very Low Bitrate
ARM® ARM926EJ-S™ Core
Support for 32-Bit and 16-Bit
(Thumb Mode) Instruction Sets
DSP Instruction Extensions and Single-Cycle MAC
ARM® Jazelle Technology
Embedded ICE-RT Logic for Real-Time Debug
ARM9 Memory Architecture
16KB of Instruction Cache
8KB of Data Cache
32KB of RAM
16KB of ROM
Little Endian
Three Video Image Coprocessors
(Noise Filtering, HDVICP, MJCP) Engines
Supports a Range of Encode and Decode Operations
H.264, MPEG-4, MPEG-2, MJPEG, JPEG, WMV9 (VC-1)
Noise Filtering Engine
Video Processing Subsystem
Front End Provides:
Hardware Face Detect Engine
Hardware IPIPE for Real-Time Image Processing
Resize Engine
Resize Images From 1/16x to 8x
Separate Horizontal and Vertical Control
Two Simultaneous Output Paths
IPIPE Interface (IPIPEIF)
Image Sensor Interface (ISIF) and CMOS Imager Interface
16-Bit Parallel AFE (Analog Front End) Interface Up to 120 MHz
Glueless Interface to Common Video Decoders
BT.601/BT.656/BT.1120 Digital YCbCr 4:2:2 (8- and 16-Bit) Interface
Histogram Module
Lens Distortion Correction (LDC) Module
Hardware 3A Statistics Collection Module (H3A)
Back End Provides:
Hardware On-Screen Display (OSD)
Composite NTSC/PAL Video Encoder Output
8- and 16-Bit YCC and Up to 24-Bit RGB888 Digital Output
3 Digital-to-Analog Converters (DACs) for HD Analog Video Output
LCD Controller
BT.601/BT.656 Digital YCbCr 4:2:2 (8- and 16-Bit) Interface
Analog-to-Digital Converter (ADC)
Power Management and Real-Time Clock Subsystem (PRTCSS)
Real-Time Clock (RTC)
16-Bit Host Port Interface (HPI)
10/100 Mbps Ethernet Media Access Controller (EMAC) - Digital Media
IEEE 802.3 Compliant
Supports Media Independent Interface (MII)
Management Data I/O (MDIO) Module
Key Scan
Voice Codec
External Memory Interfaces (EMIFs)
DDR2 and mDDR SDRAM 16-Bit-Wide EMIF With 256MB of Address Space (1.8-V I/O)
Asynchronous 16- and 8-Bit-Wide EMIF (AEMIF)
Flash Memory Interfaces
NAND (8- and 16-Bit-Wide Data)
16MB of NOR Flash, SRAM
OneNAND (16-Bit-Wide Data)
Flash Card Interfaces
Two Multimedia Card (MMC) / Secure Digital (SD/SDIO)
SmartMedia/xD
Enhanced Direct Memory Access (EDMA) Controller (64 Independent Channels)
USB Port With Integrated 2.0 High-Speed PHY that Supports
USB 2.0 High-Speed Device
USB 2.0 High-Speed Host (Mini-Host, Supporting One External Device)
USB On The Go (HS-USB OTG)
Four 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers)
One 64-Bit Watchdog Timer
Two UARTs (One Fast UART With RTS and CTS Flow Control)
Five Serial Port Interfaces (SPIs) Each With Two Chip Selects
One Master or Slave Inter-Integrated Circuit (I2C) Bus™
One Multichannel Buffered Serial Port (McBSP)
I2S
AC97 Audio Codec Interface
S/PDIF Through Software
Standard Voice Codec Interface (AIC12)
SPI Protocol (Master Mode Only)
Direct Interface to T1 (E1) Framers
Time Division Multiplexed (TDM) Mode
128-Channel Mode
Four Pulse Width Modulator (PWM) Outputs
Four RTO (Real-Time Out) Outputs
Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
Boot Modes
On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, UART, USB, SPI, EMAC, or HPI
AEMIF (NOR and OneNAND)
Configurable Power-Saving Modes
Crystal or External Clock Input (Typically 19.2, 24, 27, or 36 MHz)
Flexible PLL Clock Generators
Debug Interface Support
IEEE 1149.1 (JTAG) Boundary-Scan-Compatible
ETB (Embedded Trace Buffer) With 4KB of Trace Buffer Memory
Device Revision ID Readable by ARM
338-Pin Ball Grid Array (BGA) Package
(ZCE Suffix), 0.65-mm Ball Pitch
65-nm Process Technology
3.3-V and 1.8-V I/O, 1.35-V Internal
All trademarks are the property of their respective owners.
