The SN74LS173AN is a 4-bit D-type Register with 3-state outputs. It features totem-pole 3-state outputs capable of driving highly capacitive or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide these flip-flops with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the output control circuitry is designed so that the average output disable times are shorter than the average output enable times. Gated enable inputs are provided on these devices for controlling the entry of data into the flip-flops. When both data-enable (G1\, G2\\) inputs are low, data at the D inputs are loaded into their respective flip-flops on the next positive transition of the buffered clock input. Gate output-control (M, N) inputs also are provided.
Gated output-control lines for enabling or disabling the outputs
Fully independent clock virtually eliminates restrictions for operating in parallel load
Fully independent clock virtually eliminates restrictions for operating in do nothing (hold)
