The SN65LVDS84AQDGG is a Flatlink Transmitter contains three 7-bit parallel-load serial-out shift registers and four low-voltage differential signalling (LVDS) line drivers in a single integrated circuit. These functions allow 21-bits of single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86/86A. When transmitting, data bits D0 - D20 are each loaded into registers of the "LVDS84A upon the falling edge. The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN. The "LVDS84A requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s).
21:3 Data channel compression at up to 196Mbps throughput
Suited for SVGA, XGA or SXGA data transmission from controller to display with very low EMI
Consumes less than 0.54mW when disabled
No external components required for PLL
Outputs meet or exceed the requirements of ANSI EIA/TIA-644 standard
SSC tracking capability of 3% centre spread at 50kHz modulation frequency
