The SN65DSI84 DSI to FlatLink™ bridge features a single-channel MIPI® D-PHY receiver front-end configuration with 4 lanes per channel operating at 1 Gbps per lane; a maximum input bandwidth of 4 Gbps. The bridge decodes MIPI® DSI 18bpp RGB666 and 24 bpp RGB888 packets and converts the formatted video data stream to a FlatLink™ compatible LVDS output operating at pixel clocks operating from 25 MHz to 154 MHz, offering a Dual Link LVDS, Single-Link LVDS interface with four data lanes per link.
Features
• Implements MIPI® D-PHY Version 1.00.00
Physical Layer Front-End and Display Serial
Interface (DSI) Version 1.02.00
• Single Channel DSI Receiver Configurable for One, Two, Three, or Four D-PHY Data Lanes Per Channel Operating up to 1 Gbps Per Lane
• Supports 18 bpp and 24-bpp DSI Video Packets with RGB666 and RGB888 Formats
• Suitable for 60-fps WUXGA 1920 × 1200 Resolution at 18-bpp and 24-bpp Color, 60 fps 1366 × 768 at 18 bpp and 24 bpp
• FlatLink™ Output Configurable for Single-Link or Dual-Link LVDS
• Supports Single Channel DSI to Dual-Link LVDS Operating Mode
• LVDS Output Clock Range of 25 MHz to 154 MHz in Dual-Link or Single-Link Modes
• LVDS Pixel Clock May be Sourced from Free-Running Continuous D-PHY Clock or External Reference Clock (REFCLK)
• 1.8-V Main VCC Power Supply
• Low Power Features Include SHUTDOWN Mode, Reduced LVDS Output Voltage Swing, Common Mode, and MIPI Ultra-Low Power State (ULPS) Support
• LVDS Channel SWAP, LVDS PIN Order Reverse Feature for Ease of PCB Routing
