The MPC5566 microcontroller (MCU) is a member of the MPC5500 family of microcontrollers built on the Power Architecture embedded technology. This family of parts has many new features coupled with high performance CMOS technology to provide substantial reduction of cost per feature and significant performance improvement over the MPC500 family.
The host processor core of this device complies with the Power Architecture embeddedcategory that is 100% user-mode compatible (including floating point library) with the original PowerPC instruction set.The embedded architecture enhancements improve the performance in embedded applications. The core also has additional instructions, including digital signal processing (DSP)
instructions, beyond the original PowerPC instruction set.
The MPC5500 family of parts contains many new features coupled with high performance CMOS
technology to provide significant performance improvement over the MPC565x.
The host processor core of the MPC5566 also includes an instruction set enhancement allowing variable length encoding (VLE). This allows optional encoding of mixed 16- and 32-bit instructions. With this enhancement, it is possible to significantly reduce the code size footprint.
The MPC5566 has two levels of memory hierarchy. The fastest accesses are tothe 32-kilobytes (KB)
unified cache. The next level in the hierarchy contains the 128-KB on-chip internal SRAM and three-megabytes (MB) internal flash memory. The internal SRAM and flash memory hold instructions and data. The external bus interface is designed to support most of the standard memories used with the MPC5xx family.
