* Functional replacement for LPC23xx/24xx and LPC178x/7x family devices. * ARM Cortex-M4 core: * ARM Cortex-M4 processor, running at frequencies of up to 120 MHz. * ARM Cortex-M4 built-in Memory Protection Unit (MPU) supporting eight regions. * ARM Cortex-M4 built-in Nested Vectored Interrupt Controller (NVIC). * Hardware floating-point unit (not all versions). * Non-maskable Interrupt (NMI) input. * JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watchpoints. * System tick timer. * System: * Multilayer AHB matrix interconnect provides a separate bus for each AHB master.AHB masters include the CPU, and General Purpose DMA controller. Thisinterconnect provides communication with no arbitration delays unless two mastersattempt to access the same slave at the same time. * Split APB bus allows for higher throughput with fewer stalls between the CPU andDMA. A single level of write buffering allows the CPU to continue without waiting forcompletion of APB writes if the APB was not already busy. * Embedded Trace Macrocell (ETM) module supports real-time trace. * Boundary scan for simplified board testing. * Memory: * 512 kB on-chip flash program memory with In-System Programming (ISP) andIn-Application Programming (IAP) capabilities. The combination of an enhancedflash memory accelerator and location of the flash memory on the CPU localcode/data bus provides high code performance from flash. * Up to 96 kB on-chip SRAM includes:64 kB of main SRAM on the CPU with local code/data bus for high-performanceCPU access.Two 16 kB peripheral SRAM blocks with separate access paths for higherthroughput. These SRAM blocks may be used for DMA memory as well as forgeneral purpose instruction and data storage. * Up to 4032 byte on-chip EEPROM. * External Memory Controller (EMC) provides support for asynchronous static memorydevices such as RAM, ROM and flash, as well as dynamic memories such as singledata rate SDRAM. * Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayermatrix that can be used with the SSP, I2S, UART, CRC engine, Analog-to-Digital andDigital-to-Analog converter peripherals, timer match signals, GPIO, and formemory-to-memory transfers. * Serial interfaces: * Quad SPI Flash Interface (SPIFI) with four lanes and up to 40 MB per second. * Ethernet MAC with MII/RMII interface and associated DMA controller. Thesefunctions reside on an independent AHB. * USB 2.0 full-speed dual port device/host/OTG controller with on-chip PHY andassociated DMA controller. * Five UARTs with fractional baud rate generation, internal FIFO, DMA support, andRS-485/EIA-485 support. One UART (UART1) has full modem control I/O, and oneUART (USART4) supports IrDA, synchronous mode, and a smart card modeconforming to ISO7816-3. * Three SSP controllers with FIFO and multi-protocol capabilities. The SSPinterfaces can be used with the GPDMA controller. * Three enhanced I²C-bus interfaces, one with a true open-drain output supportingthe full I²C-bus specification and Fast-mode Plus with data rates of 1 Mbit/s, twowith standard port pins. Enhancements include multiple address recognition andmonitor mode. * I²S (Inter-IC Sound) interface for digital audio input or output. It can be used withthe GPDMA. * CAN controller with two channels. * Digital peripherals: * SD/MMC memory card interface. * Up to 165 General Purpose I/O (GPIO) pins depending on the packaging, withconfigurable pull-up/down resistors, open-drain mode, and repeater mode. AllGPIOs are located on an AHB bus for fast access and support Cortex-M4bit-banding. GPIOs can be accessed by the General Purpose DMA Controller. Anypin of ports 0 and 2 can be used to generate an interrupt.
