The IS42S16320D-7BLI is a high speed CMOS, dynamic Random Access Memory (RAM) designed to operate in either 3.3 or 2.5V Vdd/Vddq memory systems, depending on the DRAM option. It is internally configured as a quad-bank DRAM with a synchronous interface. All signals are registered on the positive edge of the clock signal, CLK. All inputs and outputs are LVTTL compatible. The 512Mb SDRAM (536870912-bit) has the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide pre-charge time and the capability to randomly change column addresses on each clock cycle during burst access. A self-timed row pre-charge initiated at the end of the burst sequence is available with the AUTOpre-charge function enabled. Pre-charge one bank while accessing one of the other three banks will hide the pre-charge cycles and provide seamless, high-speed, random-access operation.
Clock frequency - 143MHz
Fully synchronous, all signals referenced to a positive clock edge
