SN74GTLP1395PWRE4 数据手册 Datasheet - TI

制造商：
TI
分类：
逻辑控制器,芯片
封装：
TSSOP-20
描述：
Two 1Bit LVTTL/GTLP Adj-Edge-Rate Bus Xcvrs w Split LVTTL Port, Fdbk Path and Selectable Polarity 20-TSSOP -40℃ to 85℃
文档：

SN74GTLP1395PWRE4 数据手册 (25 页) Hot

封装外形尺寸在 2页 16页 18页 19页

型号规则信息在 1页 2页

更新时间： 2024/05/31 07:38:23 (UTC+8)

SN74GTLP1395PWRE4 数据手册PDF (25 页)

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SN74GTLP1395PWRE4 文档

SN74GTLP1395PWRE4 数据手册

25 页, 672 KB

Two 1Bit LVTTL/GTLP Adj-Edge-Rate Bus Xcvrs w Split LVTTL Port Fdbk Path and Selectable Polarity

Two 1Bit LVTTL/GTLP Adj-Edge-Rate Bus Xcvrs w Split LVTTL Port, Fdbk Path and Selectable Polarity 20-TSSOP -40℃ to 85℃

Two 1Bit LVTTL/GTLP Adj-Edge-Rate Bus Xcvrs w Split LVTTL Port, Fdbk Path and Selectable Polarity 20-SOIC -40℃ to 85℃

Two 1Bit LVTTL/GTLP Adj-Edge- ate Bus Xcvrs w Split LVTTL Port, Fdbk Path and Selectable Polarity 20-TSSOP -40℃ to 85℃

Two 1Bit LVTTL/GTLP Adj-Edge- ate Bus Xcvrs w Split LVTTL Port, Fdbk Path and Selectable Polarity 20-SOIC -40℃ to 85℃

Bus XCVR Single 2CH 3-ST 20Pin BGA MICROSTAR JUNIOR T/R

Two 1Bit LVTTL/GTLP Adj-Edge-Rate Bus Xcvrs w Split LVTTL Port, Fdbk Path and Selectable Polarity 20-TVSOP -40℃ to 85℃

Two 1Bit LVTTL/GTLP Adj-Edge-Rate Bus Xcvrs w Split LVTTL Port, Fdbk Path and Selectable Polarity 20-SOIC -40℃ to 85℃

Two 1Bit LVTTL/GTLP Adj-Edge-Rate Bus Xcvrs w Split LVTTL Port, Fdbk Path and Selectable Polarity 20-SOIC -40℃ to 85℃

Two 1Bit LVTTL/GTLP Adj-Edge-Rate Bus Xcvrs w Split LVTTL Port, Fdbk Path and Selectable Polarity 20-TSSOP -40℃ to 85℃

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