The TMS320C67x DSP (including the TMS320C6712, TMS320C6712C, TMS320C6712D devices) are members of the floating-point DSP family in the TMS320C6000. DSP platform. The C6712, C6712C, and C6712D devices are based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.
With performance of up to 900 million floating-point operations per second (MFLOPS) at a clock rate of 150 MHz, the C6712D device is the lowest-cost DSP in the C6000 DSP platform. The C6712D DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly independent functional units. The eight functional units provide four floating-/fixed-point ALUs, two fixed-point ALUs, and two floating-/fixed-point multipliers. The C6712D can produce two MACs per cycle for a total of 300 MMACS.
The C6712D uses a two-level cache-based architecture and has a powerful and diverse set of peripherals. The Level 1 program cache (L1P) is a 32-Kbit direct mapped cache and the Level 1 data cache (L1D) is a 32-Kbit 2-way set-associative cache. The Level 2 memory/cache (L2) consists of a 512-Kbit memory space that is shared between program and data space. L2 memory can be configured as mapped memory, cache, or combinations of the two. The peripheral set includes two multichannel buffered serial ports (McBSPs), two general-purpose timers, and a glueless 16-bit external memory interface (EMIF) capable of interfacing to SDRAM, SBSRAM, and asynchronous peripherals. The C6712D device also includes a dedicated general-purpose input/output (GPIO) peripheral module.
The C6712D DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals.
The C6712D has a complete set of development tools which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.
Low-Price/High-Performance Floating-Point Digital Signal Processor (DSP): TMS320C6712D
Eight 32-Bit Instructions/Cycle
150-MHz Clock Rate
6.7-ns Instruction Cycle Time
900 MFLOPS
Advanced Very Long Instruction Word (VLIW) C67x DSP Core
Eight Highly Independent Functional Units:
Four ALUs (Floating- and Fixed-Point)
Two ALUs (Fixed-Point)
Two Multipliers (Floating- and Fixed-Point)
Load-Store Architecture With 32 32-Bit General-Purpose Registers
Instruction Packing Reduces Code Size
All Instructions Conditional
Instruction Set Features
Hardware Support for IEEE Single-Precision and Double-Precision Instructions
Byte-Addressable (8-, 16-, 32-Bit Data)
8-Bit Overflow Protection
Saturation
Bit-Field Extract, Set, Clear
Bit-Counting
Normalization
L1/L2 Memory Architecture
32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
A Dedicated General-Purpose Input/Output (GPIO) Module With 5 Pins
IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
272-Pin Ball Grid Array (BGA) Package (GDP and ZDP Suffix)
CMOS Technology
0.13-µm/6-Level Copper Metal Process
3.3-V I/Os, 1.20-V Internal
TMS320C67x and C67x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
Other trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
These values are compatible with existing 1.26V designs.
TMS320C6000 and C6000 are trademarks of Texas Instruments.
Windows is a registered trademark of the Microsoft Corporation.
Throughout the remainder of this document, the TMS320C6712D shall be referred to as its individual full device part number or abbreviated as C6712D or 12D.
