The NXP® MPC564xS family of MCUs targets the needs of automotive instrument cluster and industrial markets.
* Includes on-chip display control units that directly drives the TFT displays
* Low-power design enables dynamic power management of core and peripherals
* Offers an industry standard graphics accelerator to help drive sophisticated graphics (e.g., simulated instrument cluster needles or image warping for heads-up displays)
* Offers code compatibility with applications in the MPC560xS environment
* Supported by robust enablement ecosystem to simplify and accelerate development
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## Features
* Dual-issue, 32-bit Power Architecture Book E compliant CPU core complex (e200z4d) Memory management unit and 4 KB instruction cache
* Variable length encoding (VLE) instruction set enables significant code size reduction over conventional Book E-compliant code
* Up to 2 MB on-chip flash with flash controller
* Separate 4 x 16 KB flash block for EEPROM emulation
* Up to 64 KB on-chip SRAM with ECC
* Up to 1 MB on-chip graphics SRAM (no ECC)
* Two TFT displays up to WVGA resolution parallel data interface (PDI) for digital video input
* Sound generation and playback using PCM or DDS sources with 4-channel mixer and PWM or I2S outputs
* Stepper motor drivers with stepper stall detect for up to six gauges