The SN65LVDS100D is a 2Gbps LVDS/LVPECL/CML to LVDS Repeater/Translator formed by connecting high-speed differential receivers and drivers. The receiver accepts low-voltage differential signaling (LVDS), positive-emitter-coupled logic (PECL) or current-mode logic (CML) input signals at rates up to 2Gbps and repeats it as either an LVDS or PECL output signal. The signal path through the device is differential for low radiated emissions and minimal added jitter. The output is LVDS levels as defined by TIA/EIA-644-A. The output is compatible with 3.3V PECL levels. Both drive differential transmission lines with nominally 100R characteristic impedance. It includes an 110R differential line termination resistor for less board space, fewer components and the shortest stub length possible. It does not include the VBB voltage reference. The VBB provides a voltage reference of typically 1.35V below VCC for use in receiving single-ended input signals.
Low power alternative for the MC100EP16
Inputs electrically compatible with LVPECL, CML and LVDS signal levels
<65ps Total jitter
Low 100ps (Maximum) part-to-part skew
25mV of Receiver input threshold hysteresis over 0 to 4V input voltage range
