SN65LV1023ATIThe SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10Bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10MHz to 66MHz
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SN65LV1023ATI
制造商:
TI
制造商型号#:
SN65LV1023A
百芯编号#:
CM229374560
价格(CNY):
百芯库存:
230
个
库存地点:香港
可供应量:
189
个在库
此为供应商库存，需要与销售确认
产品描述:
The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10Bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10MHz to 66MHz
The SN65LV1023A serializer and SN65LV1224B deserializer comprise a 10-bit serdes chipset designed to transmit and receive serial data over LVDS differential backplanes at equivalent parallel word rates from 10 MHz to 66 MHz. Including overhead, this translates into a serial data rate between 120-Mbps and 792-Mbps payload encoded throughput.
Upon power up, the chipset link can be initialized via a synchronization mode with internally generated SYNC patterns or the deserializer can be allowed to synchronize to random data. By using the synchronization mode, the deserializer establishes lock within specified, shorter time parameters.
The device can be entered into a power-down state when no data transfer is required. Alternatively, a mode is available to place the output pins in the high-impedance state without losing PLL lock.
The SN65LV1023A and SN65LV1224B are characterized for operation over ambient air temperature of –40°C to 85°C.
100-Mbps to 660-Mbps Serial LVDS Data Payload Bandwidth at 10-MHz
to 66-MHz System Clock
Pin-Compatible Superset of DS92LV1023/DS92LV1224
Chipset (Serializer/Deserializer) Power Consumption <450 mW (Typ) at 66 MHz
Synchronization Mode for Faster Lock
Lock Indicator
No External Components Required for PLL
28-Pin SSOP and Space Saving 5 × 5 mm QFN Packages Available
