The NB3N4666CDTR2G is a 3.3V quad LVCMOS differential line receiver translator in 16 pin TSSOP package. The NB3N4666C receiver incorporates input fail-safe protection circuit that provides a known output voltage under input open circuit, short and terminated (100 ohm) conditions. The four independent inputs accept differential signals such as M-LVDS, LVDS, LVPECL and HCSL and translates them to a single ended 3.3V LVCMOS. The NB3N4666C also offers active-high and active-low enable/disable inputs (EN and active-low EN) that allow users to control outputs of all four receivers. These inputs enable or disable the receivers and switch outputs to an active or high impedance state respectively. The high impedance mode feature helps to reduce quiescent power consumption to less than 10mW when outputs of one or more. It is used in point-to-point data transmission, backplane receivers, clock distribution networks and multidrop buses.
Maximum clock frequency of 200MHz
25ps typical channel to channel skew and 3.3ns maximum propagation delay
Data rates up to 400Mbps (200MHz) and low power consumption
Power supply voltage of 2.97V to 3.63V (3.3V ±10%)
High impedance outputs when disabled
Low quiescent power less than 10mW
Supports open, short and terminated input fail-safe
10mA no load supply (all receivers enabled) and 3mA no load supply (all receivers disabled)
Channel to channel skew of 25ps and part to part skew of 50ps
