GENERAL DESCRIPTION nThe MACH® 5 family consists of a broad range of high-density and high-I/O Complex Programmable Logic Devices (CPLDs). The fifth-generation MACH architecture yields fast speeds at high CPLD densities, low power, and supports additional features such as in-system programmability, Boundary Scan testability, and advanced clocking options (Table 1). The MACH 5 family offers 5-V (M5-xxx) and 3.3-V (M5LV-xxx) operation. nManufactured in state-of-the-art ISO 9000 qualified fabrication facilities on E2CMOS process technologies, MACH 5 devices are available with pin-to-pin delays as fast as 5.5 ns (Table 2). The 5.5, 6.5, 7.5, 10, and 12-ns devices are compliant with the PCI Local Bus Specification.nFEATURES n◆ High logic densities and I/Os for increased logic integration n — 128 to 512 macrocell densities n — 68 to 256 I/Os n◆ Wide selection of density and I/O combinations to support most application needs n — 6 macrocell density options n — 7 I/O options n — Up to 4 I/O options per macrocell density n — Up to 5 density & I/O options for each package n◆ Performance features to fit system needs n — 5.5 ns tPD Commercial, 7.5 ns tPD Industrial n — 182 MHz fCNT n — Four programmable power/speed settings per block n◆ Flexible architecture facilitates logic design n — Multiple levels of switch matrices allow for performance-based routing n — 100% routability and pin-out retention n — Synchronous and asynchronous clocking, including dual-edge clocking n — Asynchronous product- or sum-term set or reset n — 16 to 64 output enables n — Functions of up to 32 product terms n◆ Advanced capabilities for easy system integration n — 3.3-V & 5-V JEDEC-compliant operations n — IEEE 1149.1 compliant for boundary scan testing n — 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port n — PCI compliant (-5/-6/-7/-10/-12 speed grades) n — Safe for mixed supply voltage system design n — Bus-Friendly™ Inputs & I/Os n — Individual output slew rate control n — Hot socketing n — Programmable security bit n◆ Advanced E2CMOS process provides high performance, cost effective solutions n◆ Supported by ispDesignEXPERT™ software for rapid logic development n — Supports HDL design methodologies with results optimized for MACH 5 devices n — Flexibility to adapt to user requirements n — Software partnerships that ensure customer success n◆ Lattice and Third-party hardware programming support n — LatticePRO™ software for in-system programmability support on PCs and Automated Test Equipment n — Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General
