NXP’s exclusive software-driven I/O Handler (IOH) on the LPC11U37HFBD64 gives designers the ultimate design flexibility to adapt the MCU configuration and functionality to fit application needs at any time during the design cycle. The I/O Handler is a software-driven block supported by software libraries that can be used to add performance, connectivity and flexibility to system designs. The I/O Handler can emulate serial interfaces such as UART, I²C, or I²S with no or very low additional CPU load and can off-load the CPU by performing processing-intensive functions like DMA transfers in hardware.
Software libraries available for the I/O Handler include I²S, I²C, UART, CRC, threshold ADC conversion, and DMA functionality. The libraries can be downloaded at: www.lpcware.com/ioh
It’s easy to get started with the I/O Handler:
1\. Download the free library file for the function you need at www.lpcware.com/ioh
2\. Install (on IOH hardware block)
3\. Run application
4\. It’s that easy! (For the full instruction set on using the IOH libraries, go to www.lpcware.com/ioh
In addition, the LPC11U37HFBD64 is equipped with a highly flexible and configurable full-speed USB 2.0 device controller, bringing unparalleled design flexibility and seamless integration to today’s demanding connectivity solutions.
So whether it’s deciding on communication interfaces, accommodating late design changes, or requiring more performance or power efficiency from the application, the I/O Handler gives designers the ability to save time and cost while adding functionality to meet design deadlines.
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## Features
* ARM Cortex-M0 processor, running at frequencies of up to 50 MHz
* ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC)
* Non Maskable Interrupt (NMI) input selectable from several input sources
* System tick timer
* 128 kB on-chip flash program memory
* 4 kB on-chip EEPROM data memory
* 12 kB SRAM data memory
* 16 kB boot ROM
* In-System Programming (ISP) and In-Application Programming (IAP)
* ROM-based USB drivers. Flash updates via USB supported
* ROM-based 32-bit integer division routines
* Standard JTAG (Joint Test Action Group) test interface
* Serial Wire Debug
* 54 General Purpose I/O (GPIO) pins
* Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources
* Two GPIO grouped interrupt modules enable an interrupt
* High-current source output driver (20 mA) on one pin
* High-current sink driver (20 mA) on true open-drain pins
* Four general purpose counter/timers
* Programmable Windowed WatchDog Timer (WWDT)
* 10-bit ADC with input multiplexing among eight pins
* USB 2.0 full-speed device controller
* USART with fractional baud rate generation
* Two SSP controllers with FIFO and multi-protocol capabilities
* I²C-bus interface supporting the full I²C-bus specification and Fast-mode Plus
* Software‐enabled IO‐handler for hardware emulation of serial interfaces and DMA
* Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator)
