* 20 fs additive jitter Integrated Integer-N PLL with outstanding normalized phase noise contribution of -224 dBc/Hz Clock output frequency range of 1 to 800 MHz 3 LVDS and5 LVPECL clock outputs Dedicated divider and delay blocks on each clock output Pin compatible family of clocking devices 3.15 to 3.45 V operation Package: 48 pin LLP (7.0 x 7.0 x 0.8 mm)
