The ispMACH 4000ZE series high-performance Ultra Low-power Complex Programmable Logic Device (CPLD). The new family is based on Lattice"s industry-leading ispMACH 4000 architecture. Retaining the best of the previous generation, the ispMACH 4000ZE architecture focuses on significant innovations to combine high performance with low power in a flexible CPLD family. For example, the family"s new Power Guard feature minimizes dynamic power consumption by preventing internal logic toggling due to unnecessary I/O pin activity. It combines high speed and low power with the flexibility needed for ease of design. With its robust Global Routing Pool and Output Routing Pool, this family delivers excellent First-Time-Fit, timing predictability, routing, pin-out retention and density migration. This family offers densities ranging from 32 to 256 macrocells. A user programmable internal oscillator and a timer are included in the device.
Flexible CPLD macrocells with individual clock, reset, preset and clock enable controls
Ultra-low power
Easy system integration
Up to four global OE controls
Individual local OE control per I/O pin
Excellent First-Time-Fit™ and refit
Wide input gating (36 input logic blocks) for fast counters, state machines and address decoders
