The CDCLVP1204RGTT is a highly versatile low additive Jitter Buffer can generate four copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2GHz. The CDCLVP1204 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1ps, RMS from 10kHz to 20MHz and overall output skew is as low as 15ps, making the device a perfect choice for use in demanding applications. The CDCLVP1204 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to four pairs of differential LVPECL clock outputs (OUT0, OUT3) with minimum skew for clock distribution. It can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS or LVCMOS/LVTTL.
2:4 Differential buffer
Selectable clock inputs through control terminal
Universal Inputs can accept LVPECL, LVDS and LVCMOS/LVTTL
Four LVPECL outputs
2GHz Maximum clock frequency
45mA Maximum core current consumption
<100fs Very low additive jitter
15ps Maximum output skew
Green product and no Sb/Br
Device has limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
