The ADC10065 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 65 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to provide a complete conversion solution, and to minimize power consumption, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full power bandwidth of 400 MHz. Operating on a single 3.0V power supply, this device consumes just 68.4 mW at 65 MSPS, including the reference current. The Standby feature reduces power consumption to just 14 .1 mW.
Features
■ Single +3.0V operation
■ Selectable 2.0 V P-P, 1.5 VP-P, or 1.0 VP-P full-scale input swing
■ 400 MHz −3 dB input bandwidth
■ Low power consumption
■ Standby mode
■ On-chip reference and sample-and-hold amplifier
■ Offset binary or two’s complement data format
■ Separate adjustable output driver supply to accommodate 2.5V and 3.3V logic families
