The AD9545 supports existing and emerging ITU standards for the delivery of frequency, phase, and time of day over service provider packet networks.
The 10 clock outputs of the AD9545 are synchronized to any one of up to four input references. The digital phase-locked loops (PLLs) reduce timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail.
The AD9545 is available in a 48-lead LFCSP (7 mm × 7 mm) package and operates over the −40°C to +85°C temperature range.
Applications
GPS, PTP (IEEE-1588), and SyncE jitter cleanup and synchronization
Optical transport networks (OTN), SDH, Carrier Ethernet, and macro and small cell base stations.
OTN mapping/demapping with jitter cleaning
Small base station clocking, including baseband and radio
Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient control
JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking
Cable infrastructures
Carrier Ethernet
### Features and Benefits
Dual DPLL synchronizes 1 Hz to 500 MHz physical layer clocks providing frequency translation with jitter cleaning of noisy references
