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November 1988
Revised December 1998
74ACT715•74ACT715-R Programmable Video Sync Generator
© 1999 Fairchild Semiconductor Corporation DS010137.prf www.fairchildsemi.com
74ACT715•74ACT715-R
Programmable Video Sync Generator
General Description
The ACT715 and ACT715-R are 20-pin TTL-input compati-
ble devices capable of generating Horizontal, Vertical and
Composite Sync and Blank signals for televisions and
monitors. All pulse widths are completely definable by the
user. The devices are capable of generating signals for
both interlaced and noninterlaced modes of operation.
Equalization and serration pulses can be introduced into
the Composite Sync signal when needed.
Four additional signals can also be made available when
Composite Sync or Blank are used. These signals can be
used to generate horizontal or vertical gating pulses, cursor
position or vertical Interrupt signal.
These devices make no assumptions concerning the sys-
tem architecture. Line rate and field/frame rate are all a
function of the values programmed into the data registers,
the status register, and the input clock frequency.
The ACT715 is mask programmed to default to a Clock
Disable state. Bit 10 of the Status Register, Register 0,
defaults to a logic “0”. This facilitates (re)programming
before operation.
The ACT715-R is the same as the ACT715 in all respects
except that the ACT715-R is mask programmed to default
to a Clock Enabled state. Bit 10 of the Status Register
defaults to a logic “1”. Although completely (re)programma-
ble, the ACT715-R version is better suited for applications
using the default 14.31818 MHz RS-170 register values.
This feature allows power-up directly into operation, follow-
ing a single CLEAR pulse.
Features
■ Maximum Input Clock Frequency > 130 MHz
■ Interlaced and non-interlaced formats available
■ Separate or composite horizontal and vertical Sync and
Blank signals available
■ Complete control of pulse width via register
programming
■ All inputs are TTL compatible
■ 8 mA drive on all outputs
■ Default RS170/NTSC values mask programmed into
registers
■ ACT715-R is mask programmed to default to a Clock
Enable state for easier start-up into 14.31818 MHz
RS170 timing
Ordering Code:
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Assignment for DIP and SOIC
FACT is a trademark of Fairchild Semiconductor Corporation.
Order Number Package Number Package Description
74ACT715SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74ACT715PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
74ACT715-RSC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74ACT715-RPC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
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