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EPM7096LC68-12 数据手册 Datasheet - Altera

更新时间： 2023/12/03 23:47:46 (UTC+8)

EPM7096LC68-12 数据手册PDF (66 页)

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EPM7096LC68-12 文档

EPM7096LC68-12 用户编程手册

Altera

66 页, 1487 KB

Altera

Programmable logic , 64 macrocells, 4 logic array blocks, 36 I/O pins, 10ns

Altera

CPLD MAX 7000 Family 1.8K Gates 96 Macro Cells 76.9MHz 5V 84Pin PLCC

Altera

CPLD MAX 7000 Family 1.8K Gates 96 Macro Cells 125MHz 5V 100Pin PQFP

Altera

CPLD MAX 7000 Family 1.8K Gates 96 Macro Cells 90.9MHz 5V 68Pin PLCC

Altera

CPLD MAX 7000 Family 1.8K Gates 96 Macro Cells 125MHz CMOS Technology 5V 84Pin PLCC

Altera

CPLD MAX 7000 Family 1.8K Gates 96 Macro Cells 76.9MHz 5V 68Pin PLCC

Altera

CPLD MAX 7000 Family 1.8K Gates 96 Macro Cells 76.9MHz 5V 100Pin PQFP

Altera

CPLD MAX 7000 Family 1.8K Gates 96 Macro Cells 90.9MHz 5V 84Pin PLCC

Altera

CPLD MAX 7000 Family 1.8K Gates 96 Macro Cells 100MHz CMOS Technology 5V 100Pin PQFP CPLD MAX 7000 Family 1.8K Gates...

Altera

CPLD MAX 7000 Family 1.8K Gates 96 Macro Cells 125MHz 5V 68Pin PLCC

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