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CD74HC112PWT 数据手册 Datasheet - TI

更新时间： 2023/11/28 10:22:41 (UTC+8)

CD74HC112PWT 数据手册PDF (20 页)

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CD74HC112PWT 文档

CD74HC112PWT 数据手册

20 页, 750 KB

CD74HC112PWT 其它数据手册

2 页, 56 KB

High Speed CMOS Logic Dual Negative-Edge-Triggered J-K Flip-Flops with Set and Reset

Flip Flop JK-Type Neg-Edge 2Element 16Pin PDIP Tube

TEXAS INSTRUMENTS CD74HC112PWR Flip-Flop, Complementary, Differential, Negative Edge, 74HC112, JK, 14ns, 60MHz, 5.2mA, TSSOP

Flip Flop JK-Type Neg-Edge 2Element 16Pin TSSOP Tube

Flip-Flop, Complementary, Differential, Negative Edge, 74HC112, JK, 14ns, 60MHz, 5.2mA, SOIC

Flip Flop JK-Type Neg-Edge 2Element 16Pin TSSOP T/R

Flip Flop JK-Type Neg-Edge 2Element 16Pin SOP T/R

Flip Flop JK-Type Neg-Edge 2Element 16Pin SOIC T/R

J-K Flip-Flop, HC/UH Series, 2-Func, Negative Edge Triggered, 2Bit, Complementary Output, CMOS, PDSO16

Flip Flop JK-Type Neg-Edge 2Element 16Pin TSSOP T/R

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