* Common clock and master reset * Eight positive edge-triggered D-type flip-flops * Complies with JEDEC standard no. 7A * Input levels: * For 74HC377: CMOS level * For 74HCT377: TTL level * ESD protection: * HBM JESD22-A114F exceeds 2000V * MM JESD22-A115-A exceeds 200V. * Multiple package options * Specified from -40℃ to +85℃ and from -40℃ to +125℃
* Common clock and master reset * Eight positive edge-triggered D-type flip-flops * Complies with JEDEC standard no. 7A * Input levels: * For 74HC377: CMOS level * For 74HCT377: TTL level * ESD protection: * HBM JESD22-A114F exceeds 2000V * MM JESD22-A115-A exceeds 200V. * Multiple package options * Specified from -40℃ to +85℃ and from -40℃ to +125℃