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TMS320DM8127
SPRS712C –JUNE 2012–REVISED MARCH 2014
TMS320DM8127 DaVinci™ Video Processors
Check for Samples: TMS320DM8127
1 High-Performance System-on-Chip (SoC)
1.1 Features
1
– Image Sensor Interface (ISIF) for Handling
• High-Performance DaVinci Video Processors
Image and Video Data From the Camera
– Up to 1-GHz ARM® Cortex®-A8 RISC Core
Sensor
– Up to 750-MHz C674x VLIW DSP
– Image Pipe Interface (IPIPEIF) for Image and
– Up to 6000 MIPS and 4500 MFLOPS
Video Data Connection Between Camera
– Fully Software-Compatible with C67x+, C64x+
Sensor, ISIF, IPIPE, and DRAM
• ARM Cortex-A8 Core
– Image Pipe (IPIPE) for Real-Time Image and
– ARMv7 Architecture
Video Processing
• In-Order, Dual-Issue, Superscalar Processor
– Resizer
Core
• Resizing Image and Video From 1/16x to 8x
• Neon™ Multimedia Architecture
• Generating Two Different Resizing Outputs
• Supports Integer and Floating Point
Concurrently
• Jazelle® RCT Execution Environment
– Hardware 3A Engine (H3A) for Generating Key
• ARM Cortex-A8 Memory Architecture
Statistics for 3A (AE, AWB, and AF) Control
– 32KB of Instruction and Data Caches
• Face Detect Engine (FD)
– 256KB of L2 Cache
– Hardware Face Detection for up to 35 Faces at
OPP100
– 64KB of RAM, 48KB of Boot ROM
• Programmable High-Definition Video Image
• TMS320C674x Floating-Point VLIW DSP
Coprocessing (HDVICP v2) Engine
– 64 General-Purpose Registers (32-Bit)
– Encode, Decode, Transcode Operations
– Six ALU (32-/40-Bit) Functional Units
– H.264, MPEG-2, VC-1, MPEG-4, SP/ASP,
• Supports 32-Bit Integer, SP (IEEE Single
JPEG/MJPEG
Precision/32-Bit) and DP (IEEE Double
• Media Controller
Precision/64-Bit) Floating Point
– Controls the HDVPSS and ISS
• Supports up to Four SP Adds Per Clock and
Four DP Adds Every Two Clocks
• Endianness
• Supports up to Two Floating-Point (SP or
– ARM and DSP Instructions/Data – Little Endian
DP) Approximate Reciprocal or Square Root
• HD Video Processing Subsystem (HDVPSS)
Operations Per Cycle
– One 165-MHz HD Video Capture Input
– Two Multiply Functional Units
• One 16- or 24-Bit Input, Splittable into Dual
• Mixed-Precision IEEE Floating-Point Multiply
8-Bit SD Capture Ports
Supported up to:
– Two 165-MHz HD Video Display Outputs
– 2 SP x SP → SP Per Clock
• One 16-, 24-, or 30-Bit Output and One 16-
– 2 SP x SP → DP Every Two Clocks
or 24-Bit Output
– 2 SP x DP → DP Every Three Clocks
– Composite or S-Video Analog Output
– 2 DP x DP → DP Every Four Clocks
– Macrovision® Support Available
• Fixed-Point Multiply Supports Two 32 x 32
– Digital HDMI 1.3 Transmitter With Integrated
Multiplies, Four 16 x 16-Bit Multiplies
PHY
Including Complex Multiplies, or Eight 8 x 8-
– Advanced Video Processing Features Such as
Bit Multiplies per Clock Cycle
Scan, Format, Rate Conversion
• 128KB of On-Chip Memory Controller (OCMC)
– Three Graphics Layers and Compositors
RAM
• Dual 32-Bit DDR2/DDR3 SDRAM Interfaces
• Imaging Subsystem (ISS)
– Supports up to DDR2-800 and DDR3-1066
– Camera Sensor Connection
– Up to Eight x 8 Devices Total 2GB of Total
• Parallel Connection for Raw (up to 16-Bit)
Address Space
and BT.656 or BT.1120 (8- and 16-Bit)
– Dynamic Memory Manager (DMM)
• CSI2 Serial Connection
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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