* High-Performance DaVinci Video Processors * Up to 1-GHz ARM® Cortex®-A8 RISC Core * Up to 750-MHz C674x VLIW DSP * Up to 6000 MIPS and 4500 MFLOPS * Fully Software-Compatible with C67x+, C64x+ * ARM Cortex-A8 Core * ARMv7 Architecture * In-Order, Dual-Issue, Superscalar Processor Core * Neon™ Multimedia Architecture * Supports Integer and Floating Point * Jazelle® RCT Execution Environment * ARM Cortex-A8 Memory Architecture * 32KB of Instruction and Data Caches * 256KB of L2 Cache * 64KB of RAM, 48KB of Boot ROM * TMS320C674x Floating-Point VLIW DSP * 64 General-Purpose Registers (32-Bit) * Six ALU (32-/40-Bit) Functional Units * Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP(IEEE Double Precision/64-Bit) Floating Point * Supports up to Four SP Adds Per Clock and Four DP Adds Every TwoClocks * Supports up to Two Floating-Point (SP or DP) Approximate Reciprocal orSquare Root Operations Per Cycle * Two Multiply Functional Units * Mixed-Precision IEEE Floating-Point Multiply Supported up to: * 2 SP x SP → SP Per Clock * 2 SP x SP → DP Every Two Clocks * 2 SP x DP → DP Every Three Clocks * 2 DP x DP → DP Every Four Clocks * Fixed-Point Multiply Supports Two 32 x 32 Multiplies, Four 16 x 16-BitMultiplies Including Complex Multiplies, or Eight 8 x 8-Bit Multiplies perClock Cycle * 128KB of On-Chip Memory Controller (OCMC) RAM * Imaging Subsystem (ISS) * Camera Sensor Connection * Parallel Connection for Raw (up to 16-Bit) and BT.656 or BT.1120 (8-and 16-Bit) * CSI2 Serial Connection * Image Sensor Interface (ISIF) for Handling Image and Video Data From theCamera Sensor * Image Pipe Interface (IPIPEIF) for Image and Video Data ConnectionBetween Camera Sensor, ISIF, IPIPE, and DRAM * Image Pipe (IPIPE) for Real-Time Image and Video Processing * Resizer * Resizing Image and Video From 1/16x to 8x * Generating Two Different Resizing Outputs Concurrently * Hardware 3A Engine (H3A) for Generating Key Statistics for 3A (AE, AWB,and AF) Control * Face Detect Engine (FD) * Hardware Face Detection for up to 35 Faces at OPP100 * Programmable High-Definition Video Image Coprocessing (HDVICP v2) Engine * Encode, Decode, Transcode Operations * H.264, MPEG-2, VC-1, MPEG-4, SP/ASP, JPEG/MJPEG * Media Controller * Controls the HDVPSS and ISS * Endianness * ARM and DSP Instructions/Data – Little Endian * HD Video Processing Subsystem (HDVPSS) * One 165-MHz HD Video Capture Input * One 16- or 24-Bit Input, Splittable into Dual 8-Bit SD CapturePorts * Two 165-MHz HD Video Display Outputs * One 16-, 24-, or 30-Bit Output and One 16- or 24-BitOutput * Composite or S-Video Analog Output * Macrovision® Support Available * Digital HDMI 1.3 Transmitter With Integrated PHY * Advanced Video Processing Features Such as Scan, Format, RateConversion * Three Graphics Layers and Compositors * Dual 32-Bit DDR2/DDR3 SDRAM Interfaces * Supports up to DDR2-800 and DDR3-1066 * Up to Eight x 8 Devices Total 2GB of Total Address Space * Dynamic Memory Manager (DMM) * Programmable Multi-Zone Memory Mapping and Interleaving * Enables Efficient 2D Block Accesses * Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation andMirroring * Optimizes Interlaced Accesses
