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TMS320DM643
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SPRS269D–FEBRUARY 2005–REVISED OCTOBER 2010
TMS320DM643
Video/Imaging Fixed-Point Digital Signal Processor
Check for Samples: TMS320DM643
1 TMS320DM643 Video/Imaging Fixed-Point Digital Signal Processor
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Synchronous Memories (SDRAM, SBSRAM,
• High-Performance Digital Media Processor
ZBT SRAM, and FIFO)
– 2-, 1.67-ns Instruction Cycle Time
– 1024M-Byte Total Addressable External
– 500-, 600-MHz Clock Rate
Memory Space
– Eight 32-Bit Instructions/Cycle
• Enhanced Direct-Memory-Access (EDMA)
– 4000, 4800 MIPS
Controller (64 Independent Channels)
– Fully Software-Compatible With C64x™
• 10/100 Mb/s Ethernet MAC (EMAC)
• VelociTI.2™ Extensions to VelociTI™
– IEEE 802.3 Compliant
Advanced Very-Long-Instruction-Word (VLIW)
– Media Independent Interface (MII)
TMS320C64x™ DSP Core
– 8 Independent Transmit (TX) Channels and 1
– Eight Highly Independent Functional Units
Receive (RX) Channel
With VelociTI.2™ Extensions:
• Management Data Input/Output (MDIO)
• Six ALUs (32-/40-Bit), Each Supports
• Two Configurable Video Ports (VP1, VP2)
Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
Arithmetic per Clock Cycle – Providing a Glueless I/F to Common Video
Decoder and Encoder Devices
• Two Multipliers Support Four 16 x 16-Bit
Multiplies (32-Bit Results) per Clock – Supports Multiple Resolutions/Video Stds
Cycle or Eight 8 x 8-Bit Multiplies (16-Bit
• VCXO Interpolated Control Port (VIC)
Results) per Clock Cycle
– Supports Audio/Video Synchronization
– Load-Store Architecture With Non-Aligned
• Host-Port Interface (HPI) [32-/16-Bit]
Support
• Multichannel Audio Serial Port (McASP)
– 64 32-Bit General-Purpose Registers
– Eight Serial Data Pins
– Instruction Packing Reduces Code Size
– Wide Variety of I
2
S and Similar Bit Stream
– All Instructions Conditional
Format
• Instruction Set Features
– Integrated Digital Audio I/F Transmitter
– Byte-Addressable (8-/16-/32-/64-Bit Data)
Supports S/PDIF, IEC60958-1, AES-3, CP-430
– 8-Bit Overflow Protection Formats
– Bit-Field Extract, Set, Clear • Inter-Integrated Circuit ( I
2
C Bus™)
– Normalization, Saturation, Bit-Counting • Multichannel Buffered Serial Port
– VelociTI.2™ Increased Orthogonality – CLKS Input Not Supported
• L1/L2 Memory Architecture • Three 32-Bit General-Purpose Timers
– 128K-Bit (16K-Byte) L1P Program Cache • Sixteen General-Purpose I/O (GPIO) Pins
(Direct Mapped)
• Flexible PLL Clock Generator
– 128K-Bit (16K-Byte) L1D Data Cache (2-Way
• IEEE-1149.1 (JTAG) Boundary-
Set-Associative)
Scan-Compatible
– 2M-Bit (256K-Byte) L2 Unified Mapped
• 548-Pin Ball Grid Array (BGA) Package
RAM/Cache (Flexible RAM/Cache
(GDK and ZDK Suffixes), 0.8-mm Ball Pitch
Allocation)
• 548-Pin Ball Grid Array (BGA) Package
• Endianess: Little Endian, Big Endian
(GNZ and ZNZ Suffixes), 1.0-mm Ball Pitch
• 64-Bit External Memory Interface (EMIF)
• 0.13-µm/6-Level Cu Metal Process (CMOS)
– Glueless Interface to Asynchronous
• 3.3-V I/O, 1.2-V Internal (-500)
Memories (SRAM and EPROM) and
• 3.3-V I/O, 1.4-V Internal (-600)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Windows is a registered trademark of Microsoft Corporation.
3I
2
C Bus is a trademark of Philips Electronics N.V.
4All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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