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ADVANCEINFORMATION
TMS320C6745,TMS320C6747
www.ti.com
SPRS377D–SEPTEMBER 2008–REVISED AUGUST 2010
TMS320C6745,TMS320C6747 Fixed/Floating-point Digital Signal Processor
Check for Samples: TMS320C6745,TMS320C6747
1 TMS320C6745/6747 Fixed/Floating-point Digital Signal Processor
1.1 Features
12
(EDMA3):
• Highlights
– 2 Transfer Controllers
– 375/456-MHz C674x VLIW DSP
– 32 Independent DMA Channels
– TMS320C674x Fixed/Floating-Point VLIW
DSP Core – 8 Quick DMA Channels
– Enhanced Direct-Memory-Access Controller – Programmable Transfer Burst Size
3 (EDMA3)
• TMS320C674x Fixed/Floating-Point VLIW DSP
– 128K-Byte RAM Shared Memory (C6747 Core
Only)
– Load-Store Architecture With Non-Aligned
– Two External Memory Interfaces Support
– Three Configurable 16550 type UART – 64 General-Purpose Registers (32 Bit)
Modules
– Six ALU (32-/40-Bit) Functional Units
– LCD Controller (C6747 Only)
• Supports 32-Bit Integer, SP (IEEE Single
– Two Serial Peripheral Interfaces (SPI) Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
– Multimedia Card (MMC)/Secure Digital (SD)
• Supports up to Four SP Additions Per
– Two Master/Slave Inter-Integrated Circuit
Clock, Four DP Additions Every 2 Clocks
– One Host-Port Interface (HPI) (C6747 only)
• Supports up to Two Floating Point (SP or
– USB 1.1 OHCI (Host) With Integrated PHY
DP) Reciprocal Approximation (RCPxP)
(USB1) (C6747 Only)
and Square-Root Reciprocal
• Applications
Approximation (RSQRxP) Operations Per
– Industrial Control
Cycle
– USB, Networking
– Two Multiply Functional Units
– High-Speed Encoding
• Mixed-Precision IEEE Floating Point
– Professional Audio
Multiply Supported up to:
• Software Support
– 2 SP x SP -> SP Per Clock
– TI DSP/BIOS™
– 2 SP x SP -> DP Every Two Clocks
– Chip Support Library and DSP Library
– 2 SP x DP -> DP Every Three Clocks
• 375/456 C674x VLIW DSP
– 2 DP x DP -> DP Every Four Clocks
• C674x Instruction Set Features
• Fixed Point Multiply Supports Two 32 x
– Superset of the C67x+™ and C64x+™ ISAs
32-Bit Multiplies, Four 16 x 16-Bit
Multiplies, or Eight 8 x 8-Bit Multiplies per
– 3648/2736 C674x MIPS/MFLOPS
Clock Cycle, and Complex Multiples
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– Instruction Packing Reduces Code Size
– 8-Bit Overflow Protection
– All Instructions Conditional
– Bit-Field Extract, Set, Clear
– Hardware Support for Modulo Loop
– Normalization, Saturation, Bit-Counting
Operation
– Compact 16-Bit Instructions
– Protected Mode Operation
• C674x Two Level Cache Memory Architecture
– Exceptions Support for Error Detection and
– 32K-Byte L1P Program RAM/Cache
Program Redirection
– 32K-Byte L1D Data RAM/Cache
• 128K-Byte RAM Shared Memory (C6747 Only)
– 256K-Byte L2 Unified Mapped RAM/Cache
• 3.3V LVCMOS IOs (except for USB interfaces)
– Flexible RAM/Cache Partition (L1 and L2)
• Two External Memory Interfaces:
• Enhanced Direct-Memory-Access Controller 3
– EMIFA
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2DSP/BIOS, TMS320C6000, C6000 are trademarks of Texas Instruments.
ADVANCE INFORMATION concerns new products in the sampling
Copyright © 2008–2010, Texas Instruments Incorporated
or preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.
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