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TMS320C6742
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SPRS587B–JUNE 2009– REVISED MAY 2011
TMS320C6742 Fixed/Floating-Point DSP
Check for Samples: TMS320C6742
1 TMS320C6742 Fixed/Floating-Point DSP
1.1 Features
12
and Square-Root Reciprocal
• Highlights
Approximation (RSQRxP) Operations Per
– 200-MHz C674x Fixed/Floating-Point VLIW
Cycle
DSP
– Two Multiply Functional Units
– Enhanced Direct-Memory-Access Controller
• Mixed-Precision IEEE Floating Point
(EDMA3)
Multiply Supported up to:
– DDR2/Mobile DDR Memory Controller
– 2 SP x SP → SP Per Clock
– One Configurable UART Modules
– 2 SP x SP → DP Every Two Clocks
– One Multichannel Audio Serial Port
– 2 SP x DP → DP Every Three Clocks
– One Multichannel Buffered Serial Ports
– 2 DP x DP → DP Every Four Clocks
• 200-MHz C674x Fixed/Floating-Point VLIW DSP
• Fixed Point Multiply Supports Two 32 x
• C674x™ Instruction Set Features
32-Bit Multiplies, Four 16 x 16-Bit
– Superset of the C67x+™ and C64x+™ ISAs
Multiplies, or Eight 8 x 8-Bit Multiplies per
– Up to 1600/1200 C674x MIPS/MFLOPS
Clock Cycle, and Complex Multiples
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– Instruction Packing Reduces Code Size
– 8-Bit Overflow Protection
– All Instructions Conditional
– Bit-Field Extract, Set, Clear
– Hardware Support for Modulo Loop
– Normalization, Saturation, Bit-Counting
Operation
– Compact 16-Bit Instructions
– Protected Mode Operation
• C674x Two Level Cache Memory Architecture
– Exceptions Support for Error Detection and
– 32K-Byte L1P Program RAM/Cache
Program Redirection
– 32K-Byte L1D Data RAM/Cache
• Software Support
– 64K-Byte L2 Unified Mapped RAM/Cache
– TI DSP/BIOS™
– Flexible RAM/Cache Partition (L1 and L2)
– Chip Support Library and DSP Library
• Enhanced Direct-Memory-Access Controller 3
• 1.8V or 3.3V LVCMOS IOs (except DDR2
(EDMA3):
interfaces)
– 2 Channel Controllers
• Two External Memory Interfaces:
– 3 Transfer Controllers
– EMIFA
– 64 Independent DMA Channels
• NOR (8-/16-Bit-Wide Data)
– 16 Quick DMA Channels
• NAND (8-/16-Bit-Wide Data)
– Programmable Transfer Burst Size
• 16-Bit SDRAM With 128 MB Address
Space
• TMS320C674x Floating-Point VLIW DSP Core
– DDR2/Mobile DDR Memory Controller
– Load-Store Architecture With Non-Aligned
Support
• 16-Bit DDR2 SDRAM With 512 MB
Address Space or
– 64 General-Purpose Registers (32 Bit)
• 16-Bit mDDR SDRAM With 256 MB
– Six ALU (32-/40-Bit) Functional Units
Address Space
• Supports 32-Bit Integer, SP (IEEE Single
• One Configurable 16550 type UART Modules:
Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
– With Modem Control Signals
• Supports up to Four SP Additions Per
– 16-byte FIFO
Clock, Four DP Additions Every 2 Clocks
– 16x or 13x Oversampling Option
• Supports up to Two Floating Point (SP or
• One Serial Peripheral Interface (SPI) With
DP) Reciprocal Approximation (RCPxP)
Multiple Chip-Selects
1
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