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OMAPL137-HT
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SPRS677B –FEBRUARY 2012–REVISED FEBRUARY 2013
Low-Power Applications Processor
Check for Samples: OMAPL137-HT
1 Low-Power Applications Processor
1.1 Features
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– Bit-Field Extract, Set, Clear
• Highlights
– Normalization, Saturation, Bit-Counting
– Dual Core SoC
– Compact 16-Bit Instructions
• 300-MHz ARM926EJ-S™ RISC MPU
• C674x Two Level Cache Memory Architecture
• 300-MHz C674x™ VLIW DSP
– 32K-Byte L1P Program RAM/Cache
– TMS320C674x Fixed/Floating-Point VLIW
DSP Core – 32K-Byte L1D Data RAM/Cache
– Enhanced Direct-Memory-Access Controller – 256K-Byte L2 Unified Mapped RAM/Cache
3 (EDMA3)
– Flexible RAM/Cache Partition (L1 and L2)
– 128K-Byte RAM Shared Memory
– 1024KB L2 ROM
– Two External Memory Interfaces
• Enhanced Direct-Memory-Access Controller 3
– Two External Memory Interfaces Modules (EDMA3):
– LCD Controller – 2 Transfer Controllers
– Two Serial Peripheral Interfaces (SPI) – 32 Independent DMA Channels
– Multimedia Card (MMC)/Secure Digital (SD) – 8 Quick DMA Channels
– Two Master/Slave Inter-Integrated Circuit – Programmable Transfer Burst Size
– One Host-Port Interface (HPI) • TMS320C674x™ Fixed/Floating-Point VLIW DSP
Core
– USB 1.1 OHCI (Host) With Integrated PHY
(USB1) – Load-Store Architecture With Non-Aligned
Support
• Applications
– 64 General-Purpose Registers (32 Bit)
– Industrial Diagnostics
– Six ALU (32-/40-Bit) Functional Units
– Test and measurement
• Supports 32-Bit Integer, SP (IEEE Single
– Military Sonar/Radar
Precision/32-Bit) and DP (IEEE Double
– Medical measurement
Precision/64-Bit) Floating Point
– Professional Audio
• Supports up to Four SP Additions Per
– Down Hole Industry
Clock, Four DP Additions Every 2 Clocks
• Software Support
• Supports up to Two Floating Point (SP or
– TI DSP/BIOS™
DP) Approximate Reciprocal or Square
– Chip Support Library and DSP Library
Root Operations Per Cycle
• ARM926EJ-S Core
– Two Multiply Functional Units
– 32-Bit and 16-Bit (Thumb®) Instructions
• Mixed-Precision IEEE Floating Point
– DSP Instruction Extensions
Multiply Supported up to:
– Single Cycle MAC
– 2 SP x SP -> SP Per Clock
– ARM
®
Jazelle
®
Technology
– 2 SP x SP -> DP Every Two Clocks
– EmbeddedICE-RT™ for Real-Time Debug
– 2 SP x DP -> DP Every Three Clocks
• ARM9 Memory Architecture
– 2 DP x DP -> DP Every Four Clocks
• C674x Instruction Set Features
• Fixed Point Multiply Supports Two 32 x
32-Bit Multiplies, Four 16 x 16-Bit
– Superset of the C67x+™ and C64x+™ ISAs
Multiplies, or Eight 8 x 8-Bit Multiplies per
– Up to 3648/2736 C674x MIPS/MFLOPS
Clock Cycle, and Complex Multiples
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– Instruction Packing Reduces Code Size
– 8-Bit Overflow Protection
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2DSP/BIOS, C67x+, C64x+, TMS320C6000, C6000 are trademarks of Texas Instruments.
3ARM926EJ-S, EmbeddedICE-RT, ETM9, CoreSight are trademarks of ARM Limited.
4ARM, Jazelle are registered trademarks of ARM Limited.
5Windows is a registered trademark of Microsoft Corporation.
PRODUCTION DATA information is current as of publication date. Products conform to
Copyright © 2012–2013, Texas Instruments Incorporated
specifications per the terms of the Texas Instruments standard warranty. Production
processing does not necessarily include testing of all parameters.
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