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EP2C20Q240C8N 产品设计参考 - Altera

更新时间: 2024-06-05 16:52:50 (UTC+8)

EP2C20Q240C8N 产品设计参考

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Altera Virtual JTAG (altera_virtual_jtag) IP Core User
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The Altera Virtual JTAG (altera_virtual_jtag) megafunction IP core provides access to the PLD source
through the JTAG interface. This IP core is optimized for Altera device architectures. Using IP cores in
place of coding your own logic saves valuable design time, and offers more efficient logic synthesis and
device implementation. You can scale the IP core's size by setting parameters.
Related Information
Introduction to Altera IP Cores
The Virtual JTAG IP core allows you to create your own software solution for monitoring, updating, and
debugging designs through the JTAG port without using I/O pins on the device, and is one feature in the
On-Chip Debugging Tool Suite. The Quartus
II software or JTAG control host identifies each instance of
this IP core by a unique index. Each IP core instance functions in a flow that resembles the JTAG
operation of a device. The logic that uses this interface must maintain the continuity of the JTAG chain on
behalf the PLD device when this instance becomes active.
With the Virtual JTAG IP core you can build your design for efficient, fast, and productive debugging
solutions. Debugging solutions can be part of an evaluation test where you use other logic analyzers to
debug your design, or as part of a production test where you do not have a host running an embedded
logic analyzer. In addition to debugging features, you can use the Virtual JTAG IP core to provide a single
channel or multiple serial channels through the JTAG port of the device. You can use serial channels in
applications to capture data or to force data to various parts of your logic.
Each feature in the On-Chip Debugging Tool Suite leverages on-chip resources to achieve real time
visibility to the logic under test. During runtime, each tool shares the JTAG connection to transmit
collected test data to the Quartus II software for analysis. The tool set consists of a set of GUIs, IP core
intellectual property (IP) cores, and Tcl application programming interfaces (APIs). The GUIs provide the
configuration of test signals and the visualization of data captured during debugging. The Tcl scripting
interface provides automation during runtime.
The Virtual JTAG IP core provides you direct access to the JTAG control signals routed to the FPGA core
logic, which gives you a fine granularity of control over the JTAG resource and opens up the JTAG
resource as a general-purpose serial communication interface. A complete Tcl API is available for sending
and receiving transactions into your device during runtime. Because the JTAG pins are readily accessible
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trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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EP2C20Q240C8N 数据手册 PDF

EP2C20Q240C8N 产品设计参考
50 页, 1976 KB
EP2C20Q240C8N 其它数据手册
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EP2C20Q240C8N 产品描述及参数
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EP2C20Q240C8N 产品封装文件
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EP2C20Q240C8 数据手册 PDF

FPGA Cyclone II Family 18752 Cells 402.58MHz 90nm Technology 1.2V 240Pin PQFP
Field Programmable Gate Array, 1172 CLBs, 402.5MHz, 18752-Cell, CMOS, PQFP240, PLASTIC, QFP-240
FPGA Cyclone II Family 18752 Cells 402.58MHz 90nm Technology 1.2V 240Pin PQFP
Field Programmable Gate Array, 1172 CLBs, 402.5MHz, 18752-Cell, CMOS, PQFP240, LEAD FREE, PLASTIC, QFP-240
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