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User's Guide
SCAU039–October 2009
Low Additive Phase Noise Clock Buffer Evaluation Board
Figure 1. CDCLVP2104EVM Evaluation Board
Features:
• Easy-to-use evaluation board to fan out low phase noise clocks
• Easy device setup
• Fast configuration
• Control pins configurable through jumpers
• Board powered at +2.5-V/+3.3-V
• Single-ended or differential input clocks
• CDCLVP2104 supports eight LVPECL outputs; CDCLVP2104EVM supports four LVPECL outputs
Contents
1 General Description ......................................................................................................... 2
2 Signal Path and Control Circuitry ......................................................................................... 2
3 Getting Started .............................................................................................................. 2
4 Input Clock Selection ....................................................................................................... 2
5 Output Clock ................................................................................................................. 3
6 Schematics and Layout .................................................................................................... 3
List of Figures
1 CDCLVP2104EVM Evaluation Board .................................................................................... 1
2 CDCLVP2104EVM—Schematic .......................................................................................... 3
3 CDCLVP2104EVM—Schematic .......................................................................................... 4
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SCAU039–October 2009 Low Additive Phase Noise Clock Buffer Evaluation Board
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