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Preliminary Technical Data
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Blackfin
®
Embedded
Symmetric Multi-Processor
ADSP-BF561
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel:781/329-4700 www.analog.com
Fax:781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.
FEATURES
Dual Symmetric 600 Mhz High Performance Blackfin Core
328 KBytes of On-chip Memory (See Memory Info on Page 3)
Each Blackfin Core Includes:
Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video ALUs,
40-Bit Shifter
RISC-Like Register and Instruction Model for Ease of Pro-
gramming and Compiler-Friendly Support
Advanced Debug, Trace, and Performance- Monitoring
0.8 - 1.2V core V
DD
with On-Chip Voltage Regulation
3.3V and 2.5V Tolerant I/O
256-Ball Mini BGA and 297-Ball PBGA Package Options
PERIPHERALS
Two Parallel Input/Output Peripheral Interface Units Sup-
porting ITU-R 656 Video and Glueless Interface to ADI
Analog Front End ADCs
Two Dual Channel, Full Duplex Synchronous Serial Ports Sup-
porting Eight Stereo I
2
S Channels
Dual 16 Channel DMA Controllers and one internal memory
DMA controller
12 General Purpose 32-bit Timer/Counters, with PWM
Capability
SPI-Compatible Port
UART with Support for IrDA®
Dual Watchdog Timers
48 Programable Flags
On-Chip Phase Locked Loop Capable of 1x to 63x Frequency
Multiplication
Figure 1. Functional Block Diagram
DMA
EXTERNAL PORT
FLASH/SDRAM CONTROL
32
16
32
16
BOOT ROM
PAB
EAB
DAB
DAB
PPI PPI
VOLTAGE
REGULATOR
JTAG TEST
EMULATION
GPIO
SPI
UART
IRDA®
SPORT0
TIMERS
SPORT1
IMDMA
CONTROLLER
L1
INSTRUCTION
MEMORY
L1
DATA
MEMORY
MMU
B
L2 SRAM
128 KBYTES
CORE SYSTEM / BUS INTERFACE
L1
INSTRUCTION
MEMORY
L1
DATA
MEMORY
MMU
B
IRQ CTRL/
TIMER
IRQ CTRL/
TIMER
CONTROLLER2
DMA
CONTROLLER1
