* Optimized for 1.8V systems * Industry’s fastest low power CPLD * Densities from 32 to 512 macrocells * Industry’s best 0.18 micron CMOS CPLD * Optimized architecture for effective logic synthesis * Multi-voltage I/O operation — 1.5V to 3.3V * Advanced system features * Fastest in system programming · 1.8V ISP using IEEE 1532 (JTAG) interface * On-The-Fly Reconfiguration (OTF) * IEEE1149.1 JTAG Boundary Scan Test * Optional Schmitt trigger input (per pin) * Multiple I/O banks on all devices * Unsurpassed low power management · DataGATE external signal control * Flexible clocking modes · Optional DualEDGE triggered registers · Clock divider (÷ 2,4,6,8,10,12,14,16) · CoolCLOCK * Global signal options with macrocell control · Multiple global clocks with phase selection per macrocell · Multiple global output enables · Global set/reset * Abundant product term clocks, output enables and set/resets * Efficient control term clocks, output enables and set/resets for each macrocell and shared across function blocks * Advanced design security * Open-drain output option for Wired-OR and LED drive * Optional bus-hold, 3-state or weak pullup on select I/O pins * Optional configurable grounds on unused I/Os * Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels on all parts * SSTL2_1,SSTL3_1, and HSTL_1 on 128 macrocell and denser devices * Hot pluggable * PLA architecture * Superior pinout retention * 100% product term routability across function block * Wide package availability including fine pitch: * Chip Scale Package (CSP) BGA, Fine Line BGA, TQFP, PQFP, VQFP, and QFN packages * Pb-free available for all packages * Design entry/verification using Xilinx and industry standard CAE tools * Free software support for all densities using Xilinx® WebPACK™ tool * Industry leading nonvolatile 0.18 micron CMOS process * Guaranteed 1,000 program/erase cycles * Guaranteed 20 year data retention
