The TS3DDR32611 is a sink/source double data rate type III (PCDDR3) termination regulator with a 1% accuracy buffered reference output. It has built-in termination SPST switches that can be disconnected when the memory system undergoes lower speed operation without the need of voltage termination. Turning off these switches enables significant power saving on the memory system. The switches on-state resistance has a typical value of only 1.75Ω which helps retain signal integrity on the signal lines.
The TS3DDR32611 is powered from a 3.3V supply. The VDDQ pin takes 1.2V to 1.8V input while the output voltage at VTT pin is tracking 1/2 × VDDQ. The regulator’s VTT output is capable of sinking/sourcing up to 1A current, while the VREF pin output is 1/2VDDQ±1% × VDDQ with 5mA current sinking/sourcing capability. The TS3DDR32611 has 4 modes of operation: high speed, low speed, VREF mode and power down mode, depending on the control signals VTT_EN and ODT_EN. These different modes of operation provide flexibility to establish a memory system’s performance and power consumption.
The TS3DDR32611 is situated within a small 48 balls BGA package with only 4mm x 4mm in size, which makes it a perfect candidate to be used in mobile applications.
VDD Range – 3.0V to 3.6V
RON 1.75Ω typical
Channel Count – 26
VDDQ – Input Voltage 1.2V to 3.5V
VTT – VDDQ/2 typical with 1A sink/source capability
