description nThe TMS320C67x DSPs (including the TMS320C6711, TMS320C6711B, TMS320C6711C, TMS320C6711D devices†) compose the floating-point DSP family in the TMS320C6000 DSP platform. The C6711, C6711B, C6711C, and C6711D devices are based on the high-performance, advanced very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for multichannel and multifunction applications.n• Excellent-Price/Performance Floating-Point n Digital Signal Processors (DSPs): TMS320C67x™ (C6711, C6711B and C6711C) n − Eight 32-Bit Instructions/Cycle n − 100-, 150-, 167-, 200-MHz Clock Rates n − 10-, 6.7-, 6-, 5-ns Instruction Cycle Time n − 600, 900, 1000, 1200 MFLOPS n• Advanced Very Long Instruction Word (VLIW) C67x™ DSP Core n − Eight Highly Independent Functional Units: n − Four ALUs (Floating- and Fixed-Point) n − Two ALUs (Fixed-Point) n − Two Multipliers (Floating- and Fixed-Point) n − Load-Store Architecture With 32 32-Bit General-Purpose Registers n − Instruction Packing Reduces Code Size n − All Instructions Conditional n• Instruction Set Features n − Hardware Support for IEEE Single-Precision and Double-Precision Instructions n − Byte-Addressable (8-, 16-, 32-Bit Data) n − 8-Bit Overflow Protection n − Saturation n − Bit-Field Extract, Set, Clear n − Bit-Counting n − Normalization n• L1/L2 Memory Architecture n − 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped) n − 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative) n − 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation) n• Device Configuration n − Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot n − Endianness: Little Endian, Big Endian n• Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels) n• 32-Bit External Memory Interface (EMIF) n − Glueless Interface to Asynchronous Memories: SRAM and EPROM n − Glueless Interface to Synchronous Memories: SDRAM and SBSRAM n − 256M-Byte Total Addressable External Memory Space n• 16-Bit Host-Port Interface (HPI) n• Two Multichannel Buffered Serial Ports (McBSPs) n − Direct Interface to T1/E1, MVIP, SCSA Framers n − ST-Bus-Switching Compatible n − Up to 256 Channels Each n − AC97-Compatible n − Serial-Peripheral-Interface (SPI) Compatible (Motorola) n• Two 32-Bit General-Purpose Timers n• Flexible Phase-Locked-Loop (PLL) Clock Generator [C6711/11B] n• Flexible Software Configurable PLL-Based Clock Generator Module [C6711C] n• A Dedicated General-Purpose Input/Output (GPIO) Module With 5 Pins [C6711C] n• IEEE-1149.1 (JTAG†) n Boundary-Scan-Compatible n• 256-Pin Ball Grid Array (BGA) Package (GFN Suffix) [C6711/C6711B Only] n• 272-Pin Ball Grid Array (BGA) Package (GDP Suffix) [C6711C Only] n• CMOS Technology n − 0.13-µm/6-Level Copper Metal Process (C6711C) n − 0.18-µm/5-Level Copper Metal Process (C6711/11B) n• 3.3-V I/O, 1.20-V Internal (C6711C)‡ n• 3.3-V I/O, 1.8-V Internal (C6711B/C6711−100) n• 3.3-V I/O, 1.9-V Internal (C6711-150)
