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TMS320VC5507PGE 库存 & 价格

TMS320VC5507PGE
显示的图像仅供参考,应从产品数据表中获得准确的规格。
TMS320VC5507PGE TI
TI
  • 制造商:
    TI
  • 制造商型号#:
    TMS320VC5507PGE
  • 百芯编号#:
    CM8826759
  • 价格(CNY): ¥ 67.39
  • 百芯库存:
    228
  • 可供应量:
    168 个在库
    此为供应商库存,需要与销售确认
  • 产品类别:
    DSP,数字信号,处理器
  • 产品描述:
    DSP Fixed-Point 16Bit 200MHz 400MIPS 144Pin LQFP
  • 文档: 符合 RoHS 标准 3D模型
TMS320VC5507PGE 购买 TMS320VC5507PGE 库存和价格更新于 2024-05-18 03:50:22
  • 刷新
    器件型号: TMS320VC5507PGE
    百芯编号: CM8826759
    制造商: TI
    价格 ¥67.39
    总计: 396
    MOQ: 1
    库存地点: 香港
    发货日期: 2024/05/23 (预期 )
  • 购买
    *由于库存数量、价格不断波动,请 联系我们 获取型号最新价格和库存。

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    TMS320VC5507PGE 规格 显示相似产品 (99+)
    类型
    描述
    选择
    制造商
    TI
    类别
    DSP,数字信号,处理器
    3D模型
     3D模型
    安装方式
    Surface Mount
    引脚数
    144 Pin
    封装
    LQFP-144
    频率
    200 MHz
    电源电压(DC)
    1.55V (min)
    时钟频率
    108144200 MHz
    RAM大小
    128 KB
    位数
    16 Bit
    I/O引脚数
    7 IO
    模数转换数(ADC)
    1 ADC
    工作温度(Max)
    85 ℃
    工作温度(Min)
    -40 ℃
    显示相似产品
    TMS320VC5507PGE 数据规格书
    TMS320VC5507PGE 数据手册Datasheet
    136 Pages, 2136 KB
    2012/03/28
    查看
    TMS320VC5507PGE 产品设计参考
    139 Pages, 1983 KB
    2017/05/24
    查看
    TMS320VC5507PGE 其它数据手册Datasheet
    13 Pages, 322 KB
    2018/02/23
    查看
    TMS320VC5507PGE 其他参考文件
    1 Pages, 169 KB
    2011/06/15
    查看
    尺寸 & 包装
    类型
    描述
    长度
    20.2 mm
    宽度
    20.2 mm
    高度
    1.6 mm
    工作温度
    -40℃ ~ 85℃
    产品生命周期
    Active
    包装方式
    Tray
    符合标准
    类型
    描述
    RoHS标准
    RoHS Compliant
    含铅标准
    Lead Free
    REACH SVHC标准
    No SVHC
    出口分类
    类型
    描述
    ECCN代码
    3A991.a.2
    产品概述
    • The TMS320VC5507 fixed-point digital signal processor (DSP) is based on the TMS320C55x DSP generation CPU processor core. The C55x™ DSP architecture achieves high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.
    • The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit × 17-bit multiplication in a single cycle. A central 40-bit arithmetic/logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.
    • The C55x DSP generation supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The Program Unit decodes the instructions, directs tasks to AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.
    • The 128K bytes of on-chip memory on 5507 is sufficient for many hand-held appliances, portable GPS systems, wireless speaker phones, portable PDAs, and gaming devices. Many of these appliances typically require 64K bytes or more on-chip memory but less than 128K bytes of memory, and need to operate in standby mode for more than 60% to 70% of time. For the applications which require more than 128K bytes of on-chip memory but less than 256K bytes of on-chip memory, Texas Instruments (TI) offers the TMS320VC5509A device, which is based on the TMS320C55x DSP core.
    • The general-purpose input and output functions and the 10-bit A/D provide sufficient pins for status, interrupts, and bit I/O for LCDs, keyboards, and media interfaces. The parallel interface operates in two modes, either as a slave to a microcontroller using the HPI port or as a parallel media interface using the asynchronous EMIF. Serial media is supported through three McBSPs.
    • The 5507 peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories like EPROM and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM. Additional peripherals include Universal Serial Bus (USB), real-time clock, watchdog timer, and I2C multi-master and slave interface. Three full-duplex multichannel buffered serial ports (McBSPs) provide glueless interface to a variety of industry-standard serial devices, and multichannel communication with up to 128 separately enabled channels. The enhanced host-port interface (HPI) is a 16-bit parallel interface used to provide host processor access to 32K bytes of internal memory on the 5507. The HPI can be configured in either multiplexed or non-multiplexed mode to provide glueless interface to a wide variety of host processors. The DMA controller provides data movement for six independent channel contexts without CPU intervention, providing DMA throughput of up to two 16-bit words per cycle. Two general-purpose timers, up to eight dedicated general-purpose I/O (GPIO) pins, and digital phase-locked loop (DPLL) clock generation are also included.
    • The 5507 is supported by the industry’s award-winning eXpressDSP™, Code Composer Studio™ Integrated Development Environment (IDE), DSP/BIOS™, Texas Instruments’ algorithm standard, and the industry‘s largest third-party network. The Code Composer Studio IDE features code generation tools including a C Compiler and Visual Linker, simulator, RTDX™, XDS51™. emulation device drivers, and evaluation modules. The 5507 is also supported by the C55x DSP Library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip and board support libraries.

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