Description nThe F2805x Piccolo™ family of microcontrollers provides the power of the C28x™ core and Control Law nAccelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This family nis code-compatible with previous C28x-based code, as well as providing a high level of analog integration.nTMS320F2805x ( Piccolo™) MCUs nFeatures n• Highlights n– High-Efficiency 32-Bit CPU ( TMS320C28x™) n– 60-MHz Device n– Single 3.3-V Supply n– Integrated Power-on and Brown-out Resets n– Two Internal Zero-pin Oscillators n– Up to 42 Multiplexed GPIO Pins n– Three 32-Bit CPU Timers n– On-Chip Flash, SARAM, Message RAM, OTP, CLA Data ROM, Boot ROM, Secure ROM Memory n– Dual-Zone Security Module n– Serial Port Peripherals (SCI/SPI/I2C/eCAN) n– Enhanced Control Peripherals n• Enhanced Pulse Width Modulator (ePWM) n• Enhanced Capture (eCAP) n• Enhanced Quadrature Encoder Pulse (eQEP) n– Analog Peripherals n• One 12-Bit Analog-to-Digital Converter (ADC) n• One On-Chip Temperature Sensor n• Up to Seven Comparators With up to Three Integrated Digital-to-Analog Converters (DACs) n• One Buffered Reference DAC n• Up to Four Programmable Gain Amplifiers (PGAs) n• Up to Four Digital Filters n– 80-Pin Package n• High-Efficiency 32-Bit CPU ( TMS320C28x™) n– 60 MHz (16.67-ns Cycle Time) n– 16 x 16 and 32 x 32 MAC Operations n– 16 x 16 Dual MAC n– Harvard Bus Architecture n– Atomic Operations n– Fast Interrupt Response and Processing n– Unified Memory Programming Model n– Code-Efficient (in C/C++ and Assembly) n• Endianness: Little Endian n• Programmable Control Law Accelerator (CLA) n– 32-Bit Floating-Point Math Accelerator n– Executes Code Independently of the Main CPU n• Low Device and System Cost: n– Single 3.3-V Supply n– No Power Sequencing Requirement n– Integrated Power-on Reset and Brown-out Reset n– Low Power n– No Analog Support Pins n• Clocking: n– Two Internal Zero-pin Oscillators n– On-Chip Crystal Oscillator/External Clock Input n– Dynamic PLL Ratio Changes Supported n– Watchdog Timer Module n– Missing Clock Detection Circuitry n• Up to 42 Individually Programmable, Multiplexed GPIO Pins With Input Filtering n• Peripheral Interrupt Expansion (PIE) Block That Supports All Peripheral Interrupts n• Three 32-Bit CPU Timers n• Independent 16-Bit Timer in Each ePWM Module n• On-Chip Memory n– Flash, SARAM, Message RAM, OTP, CLA Data ROM, Boot ROM, Secure ROM Available n• 128-Bit Security Key and Lock n– Protects Secure Memory Blocks n– Prevents Firmware Reverse Engineering n• Serial Port Peripherals n– Three SCI (UART) Modules n– One SPI Module n– One Inter-Integrated-Circuit (I2C) Bus n– One Enhanced Controller Area Network (eCAN) Bus n• Advanced Emulation Features n– Analysis and Breakpoint Functions n– Real-Time Debug via Hardware n• 80-Pin PN Low-Profile Quad Flatpack (LQFP)
