The TMS320F240 (F240) device is a member of a family of DSP controllers based on the TMS320C2xx generation of 16-bit fixed-point digital signal processors (DSPs). This family is optimized for digital motor/motion control applications. The DSP controllers combine the enhanced TMS320 architectural design of the C2xLP core CPU for low-cost, high-performance processing capabilities and several advanced peripherals optimized for motor/motion control applications. These peripherals include the event manager module, which provides general-purpose timers and compare registers to generate up to 12 PWM outputs, and a dual10-bit analog-to-digital converter (ADC), which can perform two simultaneous conversions within 6.1us. See the functional block diagram.
High-Performance Static CMOS Technology
Includes the T320C2xLP Core CPU
Object Compatible With the TMS320C2xx
Source Code Compatible With TMS320C25
Upwardly Compatible With TMS320C5x
132-Pin Plastic Quad Flat Package (PQ Suffix)
50-ns Instruction Cycle Time
Industrial and Automotive Temperature Available
Memory
544 Words × 16 Bits of On-Chip Data/Program Dual-Access RAM
16K Words × 16 Bits of On-Chip Program Flash EEPROM
224K Words × 16 Bits of Total Memory Address Reach (64K Data, 64K Program and 64K I/O, and 32K Global Memory Space)
Event-Manager Module
12 Compare/Pulse-Width Modulation (PWM) Channels
Three 16-Bit General-Purpose Timers With Six Modes, Including Continuous Upand Up/Down Counting
Three 16-Bit Full-Compare Units With Deadband
Three 16-Bit Simple-Compare Units
Four Capture Units (Two With Quadrature Encoder-Pulse Interface Capability)
