* Highlights * High-Performance Digital Media System-On-Chip (DMSoC) * Up to 216-MHz ARM926EJ-STM Clock Rate * Digital HDTV (720p/1080i) output for connection to external encoder * Video Processing Subsystem * Hardware IPIPE for Real-Time Image Processing * Up to 14-bit CCD/CMOS Digital Interface * Histogram Module * Resize Image 1/16x to 8x * Hardware On-Screen Display * Up to 75-MHz Pixel Clock * Composite NTSC/PAL video encoder output * Peripherals include DDR and mDDR SDRAM, 2 MMC/SD/SDIO and SmartMedia Flash Card Interfaces, USB 2.0, 3 UARTs and 3 SPIs * Enhanced Direct-Memory-Access (EDMA) * Configurable Power-Saving Modes * On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, or UART * 3.3-V and 1.8-V I/O, 1.3-V Core * Debug Interface Support * Up to 104 General-Purpose I/O (GPIO) Pins * 337-Pin Ball Grid Array at 65 nm Process Technology * High-Performance Digital Media System-on-Chip * 135-, 216-MHz ARM926EJ-S™ Clock Rate * Fully Software-Compatible With ARM™ * Extended Temperature 135- and 216-MHz Devices are Available * ARM926EJ-S Core * Support for 32-Bit and 16-Bit (Thumb Mode) Instruction Sets * DSP Instruction Extensions and Single Cycle MAC * ARM® Jazelle® Technology * EmbeddedICE-RT™ Logic for Real-Time Debug * ARM9 Memory Architecture * 16K-Byte Instruction Cache * 8K-Byte Data Cache * 32K-Byte RAM * 8K-Byte ROM * Little Endian * Video Processing Subsystem * Front End Provides: * Hardware IPIPE for Real-Time Image Processing * Up to 14-bit CCD/CMOS Digital Interface * 16-/8-bit Generic YcBcR-4:2 Interface (BT.601) * 10-/8-bit CCIR6565/BT655 Interface * Up to 75-MHz Pixel Clock * Histogram Module * Resize Engine * Resize Images From 1/16x to 8x * Separate Horizontal/Vertical Control * Two Simultaneous Output Paths * Back End Provides: * Hardware On-Screen Display (OSD) * Composite NTSC/PAL video encoder output * 8-/16-bit YCC and Up to 18-Bit RGB666 Digital Output * BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface * Digital HDTV (720p/1080i)output for connection to external encoder * External Memory Interfaces (EMIFs) * DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1.8-V I/O) * Asynchronous16-/8-bit Wide EMIF (AEMIF) * Flash Memory Interfaces * NAND (8-/16-bit Wide Data) * OneNAND(16-bit Wide Data) * Flash Card Interfaces * Two Multimedia Card (MMC) / Secure Digital (SD/SDIO) * SmartMedia * Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) * USB Port with Integrated 2.0 High-Speed PHY that Supports * USB 2.0 Full and High-Speed Device * USB 2.0 Low, Full, and High-Speed Host * Three 64-Bit General-Purpose Timers (each configurable as two 32-bit timers) * One 64-Bit Watch Dog Timer * Three UARTs (One fast UART with RTS and CTS Flow Control) * Three Serial Port Interfaces (SPI) each with two Chip-Selects * One Master/Slave Inter-Integrated Circuit (I2C) Bus® * Two Audio Serial Port (ASP) * I2S and TDM I2S * AC97 Audio Codec Interface * S/PDIF via Software * Standard Voice Codec Interface (AIC12) * SPI Protocol (Master Mode Only) * Four Pulse Width Modulator (PWM) Outputs * Four RTO (Real Time Out) Outputs * Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
