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TLV320AIC3212IYZFR 库存 & 价格

TI Audio Codec 2ADC / 2DAC 32Bit 81Pin DSBGA T/R
31.38
TLV320AIC3212IYZFR
显示的图像仅供参考,应从产品数据表中获得准确的规格。
TLV320AIC3212IYZFR TI
TI
  • 制造商:
    TI
  • 制造商型号#:
    TLV320AIC3212IYZFR
  • 百芯编号#:
    CM28620800
  • 价格(CNY):
    31.38
  • 百芯库存:
    201
  • 可供应量:
    136 个在库
    此为供应商库存,需要与销售确认
  • 产品类别:
    编解码器,编码器,解码器
  • 产品描述:
    Audio Codec 2ADC / 2DAC 32Bit 81Pin DSBGA T/R
  • 文档: 3D模型
TLV320AIC3212IYZFR 购买 TLV320AIC3212IYZFR 库存和价格更新于 2025-06-13 03:50:22
  • 刷新
    器件型号: TLV320AIC3212IYZFR
    百芯编号: CM28620800
    制造商: TI
    封装: DSBGA-81
    价格
    31.38
    总计: 337
    MOQ: 1
    库存地点: 香港
    发货日期: 2025/06/18 (预期 )
  • 购买
    *由于库存数量、价格不断波动,请 联系我们 获取型号最新价格和库存。

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    TLV320AIC3212IYZFR 规格 显示相似产品 (99+)
    类型
    描述
    选择
    制造商
    TI
    类别
    编解码器,编码器,解码器
    3D模型
     3D模型
    安装方式
    Surface Mount
    引脚数
    81 Pin
    封装
    DSBGA-81
    采样率
    192 KSPS
    功耗
    5.00 mW
    输出功率
    2 W
    模数转换数(ADC)
    2 ADC
    工作温度(Max)
    85 ℃
    工作温度(Min)
    -40 ℃
    数模转换数(DAC)
    2 DAC
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    尺寸 & 包装
    类型
    描述
    工作温度
    -40℃ ~ 85℃
    产品生命周期
    Active
    包装方式
    Tape & Reel (TR)
    符合标准
    类型
    描述
    RoHS标准
    RoHS Compliant
    含铅标准
    Lead Free
    出口分类
    类型
    描述
    ECCN代码
    EAR99
    产品概述
    • The TLV320AIC3212 (also referred to as the AIC3212) device is a flexible, highly-integrated, low-power, low-voltage stereo audio codec. The AIC3212 features digital microphone inputs and programmable outputs, PowerTune capabilities, selectable audio-processing blocks, predefined and parameterizable signal processing blocks, integrated PLL, and flexible audio interfaces. Extensive register-based control of power, input and output channel configuration, gains, effects, pin-multiplexing and clocks are included, allowing the device to be precisely targeted to its application.
    • Combined with the advanced PowerTune technology, the device can execute operations from 8-kHz mono voice playback to stereo 192-kHz DAC playback, making it ideal for portable battery-powered audio and telephony applications.
    • The record path of the TLV320AIC3212 covers operations from 8-kHz mono to 192-kHz stereo recording, and contains programmable input channel configurations which cover single-ended and differential setups, as well as floating or mixing input signals. It also provides a digitally-controlled stereo microphone preamplifier and integrated microphone bias. One application of the digital signal processing blocks is removable of audible noise that may be introduced by mechanical coupling, for example, optical zooming in a digital camera. The record path can also be configured as a stereo digital microphone Pulse Density Modulation (PDM) interface typically used at 64 Fs or 128 Fs.
    • The playback path offers signal processing blocks for filtering and effects; headphone, line, receiver, and Class-D speaker outputs; flexible mixing of DAC; and analog input signals as well as programmable volume controls. The playback path contains two high-power DirectPath headphone output drivers which eliminate the need for ac coupling capacitors. A built in charge pump generates the negative supply for the ground centered headphone drivers. These headphone output drivers can be configured in multiple ways, including stereo, and mono BTL. In addition, playback audio can be routed to integrated stereo Class-D speaker drivers or a differential receiver amplifier.
    • The integrated PowerTune technology allows the device to be tuned to just the right power-performance trade-off. Mobile applications frequently have multiple use cases requiring very low-power operation while being used in a mobile environment. When used in a docked environment power consumption typically is less of a concern while lowest possible noise is important. With PowerTune the TLV320AIC3212 can address both cases.
    • The required internal clock of the TLV320AIC3212 can be derived from multiple sources, including the MCLK1 pin, the MCLK2 pin, the BCLK1 pin, the BCLK2 pin, several general purpose I/O pins or the output of the internal PLL, where the input to the PLL again can be derived from similar pins. Although using the internal fractional PLL ensures the availability of a suitable clock signal, TI does not recommend this for the lowest power settings. The PLL is highly programmable and can accept available input clocks in the range of 512 kHz to 50 MHz. To enable even lower clock frequencies, an integrated low-frequency clock multiplier can also be used as an input to the PLL.
    • The TLV320AIC3212 has a 12-bit SAR ADC converter that supports system voltage measurements. These system voltage measurements can be sourced from three dedicated analog inputs (IN1L/AUX1, IN1R/AUX2, or VBAT pins), or, alternatively, an on-chip temperature sensor that can be read by the SAR ADC.
    • The TLV320AIC3212 also features three full Digital Audio Serial Interfaces, each supporting I2S, DSP/TDM, RJF, LJF, and mono PCM formats. This enables the digital playback (DAC) and record (ADC) paths to select from three independent digital audio buses or chips.
    • The device is available in the 4.81 mm × 4.81 mm × 0.625 mm 81-Ball WCSP (YZF) package.

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    关联型号: TLV320 数据手册

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