The SN74LVC125ARGYR is a quadruple Bus Buffer Gate designed for 1.65 to 3.6V VCC operation. This device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up resistor and the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can be driven from either 3.3/5V devices. This feature allows the use of this device as a translator in a mixed 3.3/5V system environment.
Separate OE for all 4 buffers
Latch-up performance exceeds 250mA per JESD 17
Inputs accept voltages to 5.5V
4.8ns at 3.3V Propagation delay (tpd)
<0.8V at VCC = 3.3V, TA = 25°C VOLP (output ground bounce)
>2V at VCC = 3.3V, TA = 25°C VOHV (output VOH undershoot)
