The SN65LVDS348PW is a quadruple high-speed Differential Receiver with a wide common-mode input voltage range. This allows receipt of TIA/EIA-644 signals with up to 3V of ground noise or a variety of differential and single-ended logic levels. It offers flow-through architecture with all inputs on one side and outputs on the other to ease board layout and reduce crosstalk between receivers. LVDT versions of both integrate a 110R line termination resistor. This receiver also provides 3x the standard minimum common-mode noise voltage tolerance. The -4 to 5V common-mode range allows usage in harsh operating environments or accepts LVPECL, PECL, LVECL, ECL, CMOS and LVCMOS levels without level shifting circuitry. Precise control of the differential input voltage thresholds allows for inclusion of 50mV of input-voltage hysteresis to improve noise rejection. The differential input thresholds are still no more than ±50mV over the full input common-mode voltage range.
Flow-through architecture
Active failsafe assures a high-level output when an input signal is not present
