The PTN3361B is a high-speed level shifter device which converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain current-steering differential output signals, up to 1.65 Gbit/s per lane. Each of these lanes provides a level-shifting differential buffer to translate from low-swing AC-coupled differential signaling on the source side, to TMDS-type DC-coupled differential current-mode signaling terminated into 50 Ω to 3.3 V on the sink side. Additionally, the PTN3361B provides a single-ended active buffer for voltage translation of the HPD signal from 5 V on the sink side to 3.3 V on the source side and provides a channel with active buffering and level shifting of the DDC channel (consisting of a clock and a data line) between 3.3 V source-side and 5 V sink-side. The DDC channel is implemented using active I²C-bus buffer technology providing capacitive isolation, redriving and level shifting as well as disablement (isolation between source and sink) of the clock and data lines.
The low-swing AC-coupled differential input signals to the PTN3361B typically come from a display source with multi-mode I/O, which supports multiple display standards, e.g., DisplayPort, HDMI and DVI. While the input differential signals are configured to carry DVI or HDMI coded data, they do not comply with the electrical requirements of the DVI v1.0 or HDMI v1.3a specification. By using PTN3361B, chip set vendors are able to implement such reconfigurable I/Os on multi-mode display source devices, allowing the support of multiple display standards while keeping the number of chip set I/O pins low. See _Figure 1_.
The PTN3361B main high-speed differential lanes feature low-swing self-biasing differential inputs which are compliant to the electrical specifications of _DisplayPort Standard v1.1_and/or _PCI Express Standard v1.1_, and open-drain current-steering differential outputs compliant to DVI v1.0 and HDMI v1.3a electrical specifications. The I²C-bus channel actively buffers as well as level-translates the DDC signals for optimal capacitive isolation. Its I²C-bus control block also provides for optional software HDMI dongle detect by issuing a predetermined code sequence upon a read command to an I²C-bus specified address. The PTN3361B also supports power-saving modes in order to minimize current consumption when no display is active or connected.
The PTN3361B is a fully featured HDMI as well as DVI level shifter. It is functionally comparable to PTN3360B but provides additional features supporting HDMI dongle detection and active DDC buffering. For HDMI dongles, support of HDMI dongle detection via the DDC channel is mandatory, hence HDMI dongle applications should enable this feature for correct operation in accordance with DisplayPort interoperability guidelines.
PTN3361B is powered from a single 3.3 V power supply consuming a small amount of power (90 mW typ.) and is offered in a 48-terminal HVQFN48 package.
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## Features
**High-speed TMDS level shifting**
* Converts four lanes of low-swing AC-coupled differential input signals to DVI v1.0 and HDMI v1.3a compliant open-drain current-steering differential output signals
* Pin-programmable pre-emphasis feature
* TMDS level shifting operation up to 1.65 Gbit/s per lane (165 MHz character clock)
* TMDS level shifting operation up to 2.25 Gbit/s per lane (225 MHz character clock) using pre-emphasis feature
* Integrated 50 Ω termination resistors for self-biasing differential inputs
* Back-current safe outputs to disallow current when device power is off and monitor is on
* Disable feature to turn off TMDS inputs and outputs and to enter low-power state
**DDC level shifting**
* Integrated active DDC buffering and level shifting (3.3 V source to 5 V sink side)
* Rise time accelerator on sink-side DDC ports
* 0 Hz to 400 kHz I²C-bus clock frequency
* Back-power safe sink-side terminals to disallow backdrive current when power is off or when DDC is not enabled
**HDMI dongle detect support**
* Incorporates I²C slave ROM
* Responds to DDC read to address 81h with predetermined byte sequence
* Feature enabled by pin DDET (must be enabled for correct operation in accordance with DisplayPort interoperability guideline
**HPD level shifting**
* HPD non-inverting level shift from 0 V on the sink side to 0 V on the source side, or from 5 V on the sink side to 3.3 V on the source side
* Integrated 200 kΩ pull-down resistor on HPD sink input guarantees "input LOW" when no display is plugged in
* Back-power safe design on HPD_SINK to disallow backdrive current when power is off
**General**
* Power supply 3.3 V +- 10 pct
* ESD resilience to 7 kV HBM, 1 kV CDM
* Support for optional HDMI dongle detection via DDC/I²C-bus channel
* Power-saving modes (using output enable)
* Back-current-safe design on all sink-side main link, DDC and HPD terminals
* Transparent operation: no re-timing or software configuration required
## Target Applications
* DisplayPort to HDMI adapters (must enable DDET)
* DisplayPort to DVI adapters required to drive long cables
