* Core: 200 MHz (up to 330 DMIPS) microAptiv™ * 16 KB I-Cache, 4 KB D-Cache * MMU for optimum embedded OS execution * microMIPS™ mode for up to 35% smaller code size * DSP-enhanced core: - Four 64-bit accumulators - Single-cycle MAC, saturating and fractional math * Code-efficient (C and Assembly) architecture Clock Management * 0.9% internal oscillator * Programmable PLLs and oscillator clock sources * Fail-Safe Clock Monitor (FSCM) * Independent Watchdog Timers (WDT) and Deadman Timer (DMT) * Fast wake-up and start-up * Power Management * Low-power modes (Sleep and Idle) * Integrated Power-on Reset and Brown-out Reset * Memory Interfaces * 50 MHz External Bus Interface (EBI) * 50 MHz Serial Quad Interface (SQI) Audio and Graphics Interfaces * Graphics interfaces: EBI or PMP * Audio data communication: I2S, LJ, and RJ * Audio control interfaces: SPI and I2 C™ * Audio master clock: Fractional clock frequencies with USB synchronization * High-Speed (HS) Communication Interfaces (with Dedicated DMA) * USB 2.0-compliant Hi-Speed On-The-Go (OTG) controller * 10/100 Mbps Ethernet MAC with MII and RMII interface Security Features * Crypto Engine with a RNG for data encryption/decryption and authentication (AES, 3DES, SHA, MD5, and HMAC) * Advanced memory protection: - Peripheral and memory region access control * Direct Memory Access (DMA) * Eight channels with automatic data size detection * Programmable Cyclic Redundancy Check (CRC) * Advanced Analog Features * 10-bit ADC resolution and up to 48 analog inputs * Flexible and independent ADC trigger sources * Two comparators with 32 programmable voltage references * Temperature sensor with ±2°C accuracy * Communication Interfaces * Two CAN modules (with dedicated DMA channels): - 2.0B Active with DeviceNet™ addressing support * Six UART modules (25 Mbps): - Supports LIN 1.2 and IrDA® protocols * Six 4-wire SPI modules * SQI configurable as an additional SPI module (50 MHz) * Five I2 C modules (up to 1 Mbaud) with SMBus support * Parallel Master Port (PMP) * Peripheral Pin Select (PPS) to enable function remap * Timers/Output Compare/Input Capture * Nine 16-bit or up to four 32-bit timers/counters * Nine Output Compare (OC) modules * Nine Input Capture (IC) modules * PPS to enable function remap * Real-Time Clock and Calendar (RTCC) module Input/Output * 5V-tolerant pins with up to 32 mA source/sink * Selectable open drain, pull-ups, and pull-downs * External interrupts on all I/O pins * Qualification and Class B Support * AEC-Q100 REVG (Grade 2 -40°C to +105°C) Planned * AEC-Q100 REVG (Grade 1 -40°C to +125°C) Planned * Class B Safety Library, IEC 60730 * Back-up internal oscillator * Debugger Development Support * In-circuit and in-application programming * 4-wire MIPS® Enhanced JTAG interface * Unlimited software and 12 complex breakpoints * IEEE 1149.2-compatible (JTAG) boundary scan * Non-intrusive hardware-based instruction trace * Software and Tools Support * C/C++ compiler with native DSP/fractional support * MPLAB® Harmony Integrated Software Framework * TCP/IP, USB, Graphics, and mTouch™ middleware * MFi, Android™, and Bluetooth® audio frameworks * FreeRTOS™, OPENRTOS® , μC/OS™, and other popular RTOS kernels
