The PCA9509P is a level translating I²C-bus/SMBus repeater with two voltage supplies that enables processor low voltage 2-wire serial bus to interface with standard I²C-bus or SMBus I/O. While retaining all the operating modes and features of the I²C-bus system during the level shifts, it also permits extension of the I²C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling the I²C-bus or SMBus maximum capacitance of 400 pF on the higher voltage side. Port A allows a voltage range from 0.8 V to 1.5 V and is overvoltage tolerant. Port B allows a voltage range from 2.3 V to 5.5 V and is overvoltage tolerant. Both port A and port B SDA and SCL pins are high-impedance when the PCA9509P is unpowered.
The bus port B drivers are compliant with SMBus I/O levels, while port A uses an offset LOW which prevents bus lock-up and allows the bidirectional nature of the device. The output pull-down on the port A internal buffer LOW is set for approximately 0.2 VCC(A), while the input threshold of the internal buffer is set about 0.1 VCC(A) lower than that of the output voltage LOW. When the port A I/O is driven LOW internally, the LOW is not recognized as a LOW by the input. This prevents a lock-up condition from occurring. The output pull-down on the port B drives a hard LOW and the input level is set at 0.3 of SMBus or I²C-bus voltage level which enables port B to connect to any other I²C-bus devices or buffer.
The PCA9509P drivers are not enabled unless VCC(A) is above 0.7 V and VCC(B) is above 1.7 V. The enable (EN) pin can also be used to turn the drivers on and off under system control. Caution should be observed to only change the state of the EN pin when the bus is idle.
The PCA9509P is the same as the PCA9509A but without the port A internal current source to allow high value pull-up resistors to reduce current consumption in portable applications.
### Selection recommendations
The PCA9509P should be used if an external A-port pull-up resistor is required to adjust current for noise margin considerations or to reduce operating current consumption.
Table 1. Device selection recommendation
Concern
|
Recommended device
\---|---
PCA9509
PCA9509A
PCA9509P
A-port — lowest voltage
1.0 V
0.85 V
0.85 V
A-port — current source [1]
yes—1 mA
yes—270 μA
no—external pull-up
operating current [2]
< 6.1 mA
< 1.9 mA
< 0.95 mA
standby current EN = LOW
< 2 mA
< 22 μA max.
< 22 μA max.
1\. The PCA9509 current mirrors do not shut down when the device is disabled allowing instant turn-on, but at the cost of the higher standby current. The PCA9509A and PCA9509P current mirrors are turned off when disabled for lowest standby power consumption, but sufficient delay (10 μs) after enable is needed before resuming operation.
2\. Operating currents do not include the current consumed by the external pull-ups on B-port or the external pull-ups on the A-port of the PCA9509P.
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## Features
* Bidirectional buffer isolates capacitance and allows 400 pF on port B of the device
* Voltage level translation from port A (0.8 V to 1.5 V) to port B (2.3 V to 5.5 V)
* No internal current source on A port to reduce current consumption for portable applications
* Active HIGH enable input disables current mirrors to reduce standby power
* Open-drain inputs/outputs
* Lock-up free operation
* Supports arbitration and clock stretching across the repeater
* Accommodates Standard-mode and Fast-mode I²C-bus devices and multiple masters
* Powered-off high-impedance I²C-bus pins
* Operating supply voltage range of 0.8 V to 1.5 V on port A, 2.3 V to 5.5 V on port B
* All pins are 5 V tolerant with respect to ground pin
* 0 Hz to 400 kHz clock frequency
**Remark:** The maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater.
* ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
* Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
