The NB4L7210 is a Clock input crosspoint fanout distribution device selecting between one of two input clocks on each of the 10 differential output pairs. A 10 Bit Serial Data Interface programs each output MUX to asynchronously select either Input clock. CLOCK inputs can accept LVCMOS, LVTTL, LVPECL, CML, or LVDS signal levels and incorporate an internal 50 ohms on die termination resistors. SCLK, SDATA, and SLOAD input can accept single ended LVPECL, CML, LVCMOS, LVTTL signals levels. SCLK and SDATA inputs operate up to 20 MHz. SLOAD input loads and latches the output select data. The SDATAOUT pin permits cascading multiple devices. Outputs are optimized for minimal output-to-output skew and low jitter
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Typical Input Clock Frequency > 2 GHz
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High Frequency
200 ps Typical Rise and Fall Times
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Critical Edge Placement
800 ps Typical Propagation Delay
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Output to Output Skew 150 ps
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2 ps RMS Typical Additive Clock Jitter
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Operating Range: VCC = 2.375 V to 3.6 V with VEE = 0 V
