The NB3V8312C is a high performance, low skew LVCMOS fanout buffer which can distribute 12 ultra-low jitter clocks from an LVCMOS/LVTTL input up to 250 MHz. The 12 LVCMOS output pins drive 50Ωseries or parallel terminated transmission lines. The outputs can also be disabled to a high impedance (tri-stated) via the OE input, or enabled when High. The NB3V8312C provides an enable input, CLK_EN pin, which synchronously enables or disables the clock outputs while in the LOW state. Since this input is internally synchronized to the input clock, changing only when the input is LOW, potential output glitching or runt pulse generation is eliminated. Separate VDD core and VDDO output supplies allow the output buffers to operate at the same supply as the VDD (VDD = VDDO) or from a lower supply voltage. Compared to single-supply operation, dual supply operation enables lower power consumption and output-level compatibility. The VDD core supply voltage can be set to 3.3 V, 2.5 V or 1.8 V, while the VDDO output supply voltage can be set to 3.3 V, 2.5 V, or 1.8 V, with the constraint that VDD >/= VDDO.
Features
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VDD core supply voltage can be set to 3.3 V, 2.5 V or 1.8 V
VDDO output supply voltage can be set to 3.3 V, 2.5 V, or 1.8 V, with the constraint that VDD >/= VDDO
