Single 2−Input Exclusive OR Gate ；Features High Speed: tPD = 3.5 ns (Typ) @VCC = 5 V Low Power Dissipation: ICC = 1uA (Max) @TA = 25°C Power Down Protection Provided on Inputs Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families Chip Complexity: FETs = 54 Pb−Free Packages are Available
