2−Input NAND Schmitt−Trigger ;Features High Speed: tPD = 3.6 ns (Typ) @VCC = 5.0 V Low Power Dissipation: ICC = 1.0 uA (Max) @TA = 25°C Power Down Protection Provided on Inputs Balanced Propagation Delays Pin and Function Compatible with Other Standard Logic Families Chip Complexity: FETs = 68; Equivalent Gates = 16